22-Elec-A4 Digital Systems and Computers · May 2013

Question 2 of 6: Asynchronous Binary and Decade Counters

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Question 2: Asynchronous Binary and Decade Counters (12 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Toggle (T) flip-flops with the excitation behaviour printed on the last page of the paper — $Q^{+} = Q$ when $T = 0$ and $Q^{+} = \overline{Q}$ when $T = 1$ — and an asynchronous (ripple) architecture, in which only the first stage sees the system clock and each subsequent stage is clocked by the preceding stage's output.

Find. The two state-transition tables and the two ripple-counter schematics, the second obtained from the first by adding decoding logic that truncates the count.

Approach. Exploit the defining property of a natural binary up-count: bit $Q_k$ toggles precisely when all lower bits roll over from 1 to 0. In a ripple counter this condition is produced by the wiring rather than by logic — each stage's own falling edge is the next stage's clock — so every $T$ input is tied permanently to logic 1. The decade counter is then the same hardware plus a NAND gate that detects the first illegal state and asynchronously clears the chain.

1. (a) State-transition table for the modulo-16 counter. With $Q_3$ the most significant bit, the present state simply increments:

   Present $Q_3Q_2Q_1Q_0$	Next $Q_3^{+}Q_2^{+}Q_1^{+}Q_0^{+}$	$T_3T_2T_1T_0$	Present	Next	$T_3T_2T_1T_0$
   0000	0001	0001	1000	1001	0001
   0001	0010	0011	1001	1010	0011
   0010	0011	0001	1010	1011	0001
   0011	0100	0111	1011	1100	0111
   0100	0101	0001	1100	1101	0001
   0101	0110	0011	1101	1110	0011
   0110	0111	0001	1110	1111	0001
   0111	1000	1111	1111	0000	1111

   The $T$ columns are the bitwise exclusive-OR of present and next state, i.e. the list of bits that must change. Reading them down, $T_0$ is 1 in every row, $T_1$ is 1 whenever $Q_0 = 1$, $T_2$ whenever $Q_1Q_0 = 11$, and $T_3$ whenever $Q_2Q_1Q_0 = 111$ — the classic carry-chain condition.
2. (b) Realise the ripple counter. A synchronous design would implement those AND conditions with gates. The asynchronous design instead delivers them for free: if stage $k$ is clocked by $Q_{k-1}$ and triggers on the falling edge, then stage $k$ toggles exactly when $Q_{k-1}$ goes from 1 to 0, which happens only when all bits below it were 1 and have just rolled over. Therefore $$T_3 = T_2 = T_1 = T_0 = 1$$ and the entire counter needs no gates at all. Each stage divides the frequency of the previous one by two, so $Q_0$ runs at $f_{\text{clk}}/2$, $Q_1$ at $f_{\text{clk}}/4$, $Q_2$ at $f_{\text{clk}}/8$ and $Q_3$ at $f_{\text{clk}}/16$.
   Question 2(b) - asynchronous 4-bit binary up-counter built from T flip-flops.
3. (c) State-transition table for the decade counter. A decade counter is a modulo-10 counter: it uses the natural binary sequence but returns to zero after nine, so the six states 1010 through 1111 are never entered in normal operation.

   Present $Q_3Q_2Q_1Q_0$	Decimal	Next state	$T_3T_2T_1T_0$
   0000	0	0001	0001
   0001	1	0010	0011
   0010	2	0011	0001
   0011	3	0100	0111
   0100	4	0101	0001
   0101	5	0110	0011
   0110	6	0111	0001
   0111	7	1000	1111
   1000	8	1001	0001
   1001	9	0000	1001
   1010–1111	10–15	unused (don't care)	—

   Only the last row differs from the modulo-16 table: from 1001 the counter must jump to 0000 rather than to 1010.
4. (d) Truncate the ripple counter to modulus ten. Following the hint, keep the hardware of part (b) and add a decoder that forces the chain back to zero. Because a ripple counter cannot be steered synchronously, the standard technique is to let it enter the first illegal state 1010 for a few nanoseconds and immediately abort it through the asynchronous CLEAR inputs. The state 1010 is uniquely identified among the states the counter can actually reach by the pair $Q_3 = 1$ and $Q_1 = 1$: no legal state 0000 through 1001 has both bits set, since the only legal states with $Q_3 = 1$ are 1000 and 1001, in which $Q_1 = 0$. Hence a single two-input NAND suffices: $$\overline{\text{CLR}} = \overline{Q_3 \cdot Q_1}$$ which is logic 1 (inactive) for every legal count and drops to 0 the instant 1010 appears, clearing all four stages. $$\boxed{\,\text{Decade ripple counter} = \text{modulo-16 ripple counter} + \text{NAND}(Q_3, Q_1) \rightarrow \overline{\text{CLR}}\,}$$
   Question 2(d) - the same chain truncated to a decade counter by NAND(Q3,Q1) driving CLEAR.
5. Confirm the truncated sequence. Simulating the chain stage by stage from 0000 gives 0, 1, 2, ..., 9, then the transient 1010 which the NAND immediately erases, so the observed sequence is 0, 1, ..., 9, 0, 1, ... The output frequency at $Q_3$ is therefore $f_{\text{clk}}/10$ rather than $f_{\text{clk}}/16$, though the $Q_3$ waveform is no longer a symmetric square wave.