22-Elec-A4 Digital Systems and Computers · May 2013

Question 4 of 6: Shift Registers in a Serial Communication Port

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams, May 2013 — 07-Elec-A4 Digital Systems & Computers. Three hours, closed book (one approved Casio or Sharp calculator). Six questions are printed; any five constitute a complete exam and all questions are worth 12 marks. An excitation table for the RS/JK/T/D flip-flops and a table of basic Boolean identities are supplied on the last page of the paper. All six questions are solved below, because this set is a study resource rather than a timed sitting.

Reference texts.

M. M. Mano and M. D. Ciletti, Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th ed. — Boolean algebra (Ch. 2), combinational design (Ch. 4), synchronous sequential logic (Ch. 5), registers and counters (Ch. 6), memory and address decoding (Ch. 7).
J. F. Wakerly, Digital Design: Principles and Practices, 5th ed. — canonical forms and minimisation (Ch. 3–4), counters and shift registers (Ch. 8).
C. Hamacher, Z. Vranesic, S. Zaky and N. Manjikian, Computer Organization and Embedded Systems, 6th ed. — bus structure and addressing (Ch. 2), stacks (§2.6), memory system organisation and chip-select decoding (Ch. 8).

Convention used throughout. In the address/data expressions a prime denotes complement ($\overline{A}$ is written A′ in the figures, where SVG text cannot carry an overbar). Hexadecimal constants keep the Motorola dollar-sign notation of the exam paper, written here as $7A01 in prose so that it cannot be mistaken for a mathematics delimiter.

Question 4: Shift Registers in a Serial Communication Port (12 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A serial communication port whose processor-side interface is a parallel data bus and whose line-side interface is a single wire carrying one bit at a time. D flip-flops are to be used, with marks allocated (a) 3, (b) 3, (c) 6.

Find. Which direction of conversion belongs in which half of the port, with justification, and a single 4-bit register circuit capable of both conversions with its four classes of terminal identified.

Approach. Parts (a) and (b) are answered by tracing the direction of data flow through the port; part (c) is a structural design in which a two-to-one multiplexer in front of every D input selects between "take the neighbour's bit" (shift) and "take the bus bit" (load).

(a) Parallel-to-serial conversion belongs in the transmitting unit. The processor presents a whole character — here four bits, in a real UART eight — simultaneously on the internal data bus, because that is how words are moved inside a computer. The transmission line, by contrast, can carry only one bit at a time. The transmitter must therefore capture the parallel word in one clock and then emit its bits one after another onto the line, which is precisely the function of a parallel-to-serial shift register: parallel load followed by repeated shifting, with the serial output tied to the line driver. Loading is done once per character at the processor's convenience; shifting is done at the baud-rate clock, which is normally far slower. The register also provides the buffering that decouples the two clock domains, so the processor need not wait bit by bit while the character is sent.

(b) Serial-to-parallel conversion belongs in the receiving unit. The receiver sees the reverse situation: bits arrive one at a time on the line, but the processor expects to read a complete word from a single register in one bus cycle. The receiver therefore clocks each incoming bit into the serial input of a shift register at the recovered baud-rate clock; after the required number of shifts the character sits in the register in parallel form and its outputs are read simultaneously by the processor. Attempting to hand bits to the processor one at a time would demand an interrupt per bit and would waste bus bandwidth by a factor equal to the word length. In an actual UART this same register is where the framing bits are stripped and where the parity check is accumulated as the bits shift through.

(c) A register that does both. Both functions use the same chain of D flip-flops; only the source of each D input changes. In shift mode, $D_i$ must come from $Q_{i-1}$ (and $D_0$ from the external serial input); in load mode, $D_i$ must come from the parallel input $P_i$. A 2-to-1 multiplexer per stage, all driven by a common SHIFT/LOAD′ control line, selects between the two, and all four flip-flops share one clock so the operation is synchronous.

Define the two data paths. With the select line low (LOAD) the register performs a parallel capture in one clock edge: $$D_i = P_i \quad \Rightarrow \quad Q_i^{+} = P_i, \qquad i = 0,1,2,3$$ With the select line high (SHIFT) the register performs a one-place shift per clock edge: $$D_0 = \text{SI}, \qquad D_i = Q_{i-1}\ (i = 1,2,3)$$
Combine both into one D equation per stage. Writing $S$ for the SHIFT/LOAD′ control, $$D_0 = \overline{S}\,P_0 + S\cdot\text{SI}, \qquad D_i = \overline{S}\,P_i + S\,Q_{i-1}\ (i = 1,2,3)$$ which is exactly the multiplexer function, so no separate minimisation is needed.

Identify the four terminal classes. Parallel-to-serial operation uses the parallel inputs and the serial output; serial-to-parallel operation uses the serial input and the parallel outputs. Both share the flip-flop chain.

Label in figure	Terminal	Used by
SI	(i) Serial input — the free multiplexer input of stage 0	Serial-to-parallel (receiver)
SO	(ii) Serial output — $Q_3$, the last stage	Parallel-to-serial (transmitter)
$P_0 \ldots P_3$	(iii) Parallel inputs — the load inputs of the four multiplexers	Parallel-to-serial (transmitter)
$Q_0 \ldots Q_3$	(iv) Parallel outputs — the flip-flop outputs	Serial-to-parallel (receiver)

Question 4(c) - 4-bit shift register performing both parallel-to-serial and serial-to-parallel conversion.

Sequence of operations. To transmit, assert LOAD for one clock to capture $P_3 \ldots P_0$, then assert SHIFT for four clocks while the line driver samples SO; the character leaves most-significant-bit last with this wiring. To receive, hold SHIFT and clock four times, after which $Q_3 \ldots Q_0$ hold the character and may be read in parallel. A single register can therefore serve either half of the port, and a full-duplex port simply uses two of them. $$\boxed{\,D_i = \overline{S}\,P_i + S\,Q_{i-1}\ \text{ with } Q_{-1} \equiv \text{SI};\quad \text{SO} = Q_3\,}$$

Part	Question	Answer
(a)	Parallel-to-serial register	Transmitting unit — converts a bus word into a bit stream for the line
(b)	Serial-to-parallel register	Receiving unit — assembles the arriving bit stream into a bus word
(c) i	Serial input	SI, into the shift input of the stage-0 multiplexer
(c) ii	Serial output	SO $= Q_3$
(c) iii	Parallel inputs	$P_0, P_1, P_2, P_3$ into the load inputs of the four multiplexers
(c) iv	Parallel outputs	$Q_0, Q_1, Q_2, Q_3$
(c)	Control	One SHIFT/LOAD′ line and one common clock

Topic. Universal shift registers and their role in serial data communication.

Key relations. Shift-register stage: $Q_i^{+} = D_i$; shift mode $D_i = Q_{i-1}$; parallel load $D_i = P_i$; combined $D_i = \overline{S}P_i + SQ_{i-1}$. Transmission time for an $n$-bit character at baud rate $R$ is $n/R$ seconds, independent of the processor's bus speed.

Why this works. A serial port exists to bridge two different data geometries: the wide, fast, short interconnect inside the machine and the narrow, slow, long interconnect between machines. A shift register is the natural bridge because it is simultaneously addressable in both geometries — the flip-flop outputs form a parallel word while the chain structure makes the same bits available one at a time. Adding a multiplexer per stage costs little and makes the register universal, which is why commercial parts such as the 74x194 provide exactly this structure with an additional direction control. The control line is a mode selector rather than data, so it must be stable around the clock edge; changing it mid-character corrupts the word.

Common pitfall. Answering (a) and (b) the wrong way round by thinking about the register's name rather than the data flow: "serial-to-parallel" describes what the register produces, so it belongs where parallel data is needed, that is at the processor end of the receiver. A second pitfall in part (c) is drawing two separate registers, one per direction, when the question explicitly asks for one circuit that performs both conversions.

Source. Mano & Ciletti, Digital Design, 6th ed., §6.1–6.2 (registers, shift registers, universal shift register); Hamacher et al., Computer Organization and Embedded Systems, 6th ed., Ch. 3 (serial interfaces and UART operation).

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