22-Elec-A4 Digital Systems and Computers · May 2014

Question 4 of 6: Shift Registers in a Serial Communication Port

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams, May 2014 — 07-Elec-A4 Digital Systems & Computers. Three hours, closed book (one approved Casio or Sharp calculator). Six questions are printed; any five constitute a complete exam and every question is worth 12 marks, with the per-part split given in the page-1 marking scheme (Q1 is 3+3+3+3; Q2 is 6+3+3; Q3 is 6+6; Q4 is 3+3+6; Q5 and Q6 are 4+4+4). A flip-flop excitation table for the RS/JK/T/D types and a table of 22 basic Boolean identities are supplied on the last page. All six questions are solved below, because this set is a study resource rather than a timed sitting.

Reference texts.

M. M. Mano and M. D. Ciletti, Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th ed. — Boolean algebra, canonical forms and K-maps (Ch. 2–3), combinational MSI decoders and demultiplexers (Ch. 4), synchronous sequential design and flip-flop excitation (Ch. 5), registers and counters (Ch. 6).
J. F. Wakerly, Digital Design: Principles and Practices, 5th ed. — minimisation and static timing hazards (Ch. 3–4), counters and shift registers (Ch. 8).
C. Hamacher, Z. Vranesic, S. Zaky and N. Manjikian, Computer Organization and Embedded Systems, 6th ed. — the four essential subsystems and bus structure (Ch. 1–3), serial interfaces and UART framing (§3.5), the processor register set and addressing modes (Ch. 2).
M. A. Mazidi, R. McKinlay and D. Causey, PIC Microcontroller and Embedded Systems — port-driven multiplexed seven-segment displays and LED current limiting (Ch. 12).

Notation used throughout. A bar and a prime both denote complement: \(\overline{A}\) in the mathematics and A′ in the figures, where SVG text cannot carry an overbar. In every K-map the leftmost variable is the most significant bit, so the minterm indices printed in the cells match the question’s own variable ordering.

Question 4: Shift Registers in a Serial Communication Port (12 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

A serial communication port exists to reconcile two incompatible data formats. Inside the machine, data is inherently parallel: the processor moves a whole byte or word at a time across a data bus whose width equals the register width, and every bit arrives simultaneously. On the communication link, data is inherently serial: a single signal wire (plus a return) carries the bits one after another in time, because cable, connector and isolation costs scale with conductor count while the achievable bit rate does not. The shift register is the component that performs the conversion in each direction, and the direction of conversion is what fixes where each type belongs.

(a) The parallel-to-serial register belongs in the TRANSMITTING unit. The transmitter is handed a complete character in parallel: the CPU executes a store to the transmit-data register and all eight bits are latched in one bus cycle. That character must then leave the chip as a timed sequence of bit intervals. The transmitter therefore performs a parallel load of the shift register from the internal bus, and thereafter one shift per bit time, the serial output terminal delivering the least significant bit first in the usual asynchronous (UART) framing, wrapped between a start bit and one or more stop bits. Bit timing comes from a baud-rate generator that divides the peripheral clock; the shift clock is not the CPU clock. Putting a parallel-to-serial register in the receiver would be meaningless, because the receiver never possesses the character in parallel form until after it has been assembled.

(b) The serial-to-parallel register belongs in the RECEIVING unit. The receiver sees only a voltage on one wire changing over time. Its job is the mirror image of the transmitter’s: detect the falling edge of the start bit, resynchronise its local sampling clock (typically sampling at 16 times the bit rate and taking the middle sample of each bit interval to maximise noise margin), and shift each recovered bit into the register. After the agreed number of data bits, the register holds the complete character in parallel, a stop bit is verified for framing errors, the parity is checked if enabled, and the assembled byte is transferred in one operation to the receive-data register where the CPU can read it with a single bus cycle. Because the two directions are independent, a full-duplex port contains both registers operating simultaneously, which is why a UART is drawn as two independent shift paths sharing only the baud-rate generator.

(c) A single register can do both jobs. Each D flip-flop is preceded by a two-input multiplexer controlled by a common LOAD/SHIFT line: with the control line at the shift position, each stage takes the output of its left-hand neighbour and the first stage takes the serial input; with the control line at the load position, each stage takes its own parallel input line, so the whole word is captured on one clock edge.

4-bit bidirectional-conversion shift register. (i) Serial input terminal at the left of MUX0; (ii) serial output terminal at Q3; (iii) parallel input terminals P0–P3 feeding the ‘1’ leg of each multiplexer; (iv) parallel output terminals Q0–Q3 taken directly from the flip-flop outputs.

Reading the four required identifications from the figure: the serial input terminal is the line entering the ‘0’ leg of the first multiplexer, ahead of FF0; the serial output terminal is \(Q_3\), the output of the last stage, which is also available as a parallel output; the parallel input terminals are \(P_0\) to \(P_3\), one per stage, each entering the ‘1’ leg of its multiplexer; and the parallel output terminals are \(Q_0\) to \(Q_3\) taken directly from the flip-flop outputs. Used as a transmitter the register is loaded from \(P_0\ldots P_3\) in one clock and then shifted four times while \(Q_3\) is watched; used as a receiver it is shifted four times from the serial input and then read in parallel at \(Q_0\ldots Q_3\). The common clock and the common \(\overline{CLR}\) are shown as buses.

Question 4 — final results
Part	Item	Answer
(a)	Parallel-to-serial register	Transmitting unit — parallel load from the CPU bus, then one shift per bit time out of the serial line
(b)	Serial-to-parallel register	Receiving unit — one shift per recovered bit, then a parallel read of the assembled character
(c) i	Serial input terminal	Shift-leg input of MUX0, ahead of FF0
(c) ii	Serial output terminal	\(Q_3\) (last stage)
(c) iii	Parallel input terminals	\(P_0,P_1,P_2,P_3\) into the load leg of each multiplexer
(c) iv	Parallel output terminals	\(Q_0,Q_1,Q_2,Q_3\)

Topic. Shift registers and serial/parallel conversion in a UART.

Key relations. The shift relation \(Q_i^{+}=Q_{i-1}\) with \(Q_0^{+}=\text{serial in}\); the load relation \(Q_i^{+}=P_i\); and the multiplexed stage input \(D_i=\overline{L}\,Q_{i-1}+L\,P_i\) which implements both. Character time in asynchronous framing is \((1+n_{\text{data}}+n_{\text{parity}}+n_{\text{stop}})\) bit intervals.

Why this works. The multiplexer in front of each D input is the general recipe for a mode-controlled register: whatever set of possible next values a stage may take, a multiplexer selects among them and the flip-flop commits the choice on the clock edge. Extending the same idea from two to four multiplexer inputs turns the circuit into a universal shift register that can hold, shift right, shift left, or load in parallel, which is what a 74HC194 provides. The reason the conversion direction determines placement is simply causality: a converter must be fed in the format that already exists on its input side.

Common pitfall. Answering (a) and (b) the wrong way round by reasoning about which end “has” the serial line — both ends do. The correct discriminator is where the data starts in each direction. A second pitfall in part (c) is drawing a load path that gates the clock instead of multiplexing the D inputs; gating the clock destroys synchronism and invites runt-pulse glitches.

Source. Mano & Ciletti, Digital Design 6th ed., §6.1–6.3 (shift registers, universal shift register); Hamacher et al., Computer Organization and Embedded Systems 6th ed., §3.5 (serial interfaces and UART framing).

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