22-Elec-A4 Digital Systems and Computers · May 2014

Question 5 of 6: Multiplexed Two-Digit Seven-Segment Display

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams, May 2014 — 07-Elec-A4 Digital Systems & Computers. Three hours, closed book (one approved Casio or Sharp calculator). Six questions are printed; any five constitute a complete exam and every question is worth 12 marks, with the per-part split given in the page-1 marking scheme (Q1 is 3+3+3+3; Q2 is 6+3+3; Q3 is 6+6; Q4 is 3+3+6; Q5 and Q6 are 4+4+4). A flip-flop excitation table for the RS/JK/T/D types and a table of 22 basic Boolean identities are supplied on the last page. All six questions are solved below, because this set is a study resource rather than a timed sitting.

Reference texts.

M. M. Mano and M. D. Ciletti, Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th ed. — Boolean algebra, canonical forms and K-maps (Ch. 2–3), combinational MSI decoders and demultiplexers (Ch. 4), synchronous sequential design and flip-flop excitation (Ch. 5), registers and counters (Ch. 6).
J. F. Wakerly, Digital Design: Principles and Practices, 5th ed. — minimisation and static timing hazards (Ch. 3–4), counters and shift registers (Ch. 8).
C. Hamacher, Z. Vranesic, S. Zaky and N. Manjikian, Computer Organization and Embedded Systems, 6th ed. — the four essential subsystems and bus structure (Ch. 1–3), serial interfaces and UART framing (§3.5), the processor register set and addressing modes (Ch. 2).
M. A. Mazidi, R. McKinlay and D. Causey, PIC Microcontroller and Embedded Systems — port-driven multiplexed seven-segment displays and LED current limiting (Ch. 12).

Notation used throughout. A bar and a prime both denote complement: $\overline{A}$ in the mathematics and A′ in the figures, where SVG text cannot carry an overbar. In every K-map the leftmost variable is the most significant bit, so the minterm indices printed in the cells match the question’s own variable ordering.

Question 5: Multiplexed Two-Digit Seven-Segment Display (12 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. The circuit data taken from the figure and the question statement:

Given data for the display driver
Quantity	Symbol	Value
Supply	$V_{source}$	5.0 V
PNP digit-driver saturation voltage	$V_{CE(sat)}$	0.3 V
LED forward drop when lit	$V_F$	2.0 V
Open-collector TTL inverter output-LOW voltage	$V_{OL}$	0.4 V (standard TTL guarantee)
Target segment current	$I_{LED}$	10 mA
Digit select	$PB_7$	LOW turns on T1 (10’s digit); HIGH turns on T0 through the inverter (1’s digit)
Segment lines	$PB_6\ldots PB_0$	$PB_6=g$, $PB_5=f$, …, $PB_0=a$

Find. The two Port B bytes that produce “40”, the firmware sequence that makes both digits appear lit at once, and the segment resistor $R_2$.

Approach. Establish the active polarity of each port bit from the driver topology, map the digits onto segments, then apply Kirchhoff’s voltage law around the single series path that carries the LED current.

Fix the segment polarity. The displays are common-anode, so a segment lights when its cathode is pulled LOW. Each cathode is driven by an open-collector inverter, whose output is LOW when its input is HIGH. Combining the two inversions, a segment lights when its port bit is 1: $PB_i=1\Rightarrow$ segment on.
Fix the digit-select polarity. T1 (10’s digit) is a PNP transistor whose base is driven from $PB_7$ through 5.1 kΩ, so it saturates when $PB_7=0$. T0 (1’s digit) has the same base network driven from an inverter, so it saturates when $PB_7=1$. Exactly one digit is powered at any instant — the segment lines are common to both displays, so the two digits must be time-multiplexed.
Map the digits onto segments (part a). With the standard labelling, digit 4 needs segments b, c, f, g and digit 0 needs a, b, c, d, e, f.

Segment patterns for the two digits of “40”, with the corresponding Port B byte beneath each. Lit segments are shown in red.

Assemble the two Port B bytes (part a). Writing the bits in the order $PB_7PB_6\ldots PB_0=(\text{digit select})\,g\,f\,e\,d\,c\,b\,a$:
Port B values for “40”
Digit Segments lit $PB_7$ $PB_6\;g$ $PB_5\;f$ $PB_4\;e$ $PB_3\;d$ $PB_2\;c$ $PB_1\;b$ $PB_0\;a$ Hex
10’s = 4 b, c, f, g 0 1 1 0 0 1 1 0 0x66
1’s = 0 a, b, c, d, e, f 1 0 1 1 1 1 1 1 0xBF
so the two required patterns are$$\boxed{PB=0110\,0110_2=\text{0x66 (shows 4)}\quad\text{and}\quad PB=1011\,1111_2=\text{0xBF (shows 0)}}$$
Give the firmware sequence (part b). Because only one digit is powered at a time, “40” is produced by persistence of vision rather than by a single write. The program must: (1) configure the Port B data-direction register so all eight lines are outputs; (2) build a lookup table of the seven-segment codes for 0–9 and split the number into tens and units; (3) in an endless refresh loop, write 0x66, wait a fixed digit time, write 0xBF, wait the same digit time, and repeat. A blanking write of 0x00 before each digit-select change prevents ghosting, in which a segment pattern intended for one digit is briefly lit on the other while the transistors change state. The refresh rate must exceed roughly 50 Hz to appear flicker-free; at a convenient 100 Hz the frame is 10 ms, so each digit is held for 5 ms.
Note the brightness consequence. A 50 % duty cycle halves the average luminous output relative to a statically driven display. Designers therefore often raise the peak segment current above the DC rating, within the manufacturer’s pulsed-current limit, to restore apparent brightness. The present question fixes the peak at 10 mA, so the calculation below is a peak-current calculation.

Port B values for “40”
Digit	Segments lit	\(PB_7\)	\(PB_6\;g\)	\(PB_5\;f\)	\(PB_4\;e\)	\(PB_3\;d\)	\(PB_2\;c\)	\(PB_1\;b\)	\(PB_0\;a\)	Hex
10’s = 4	b, c, f, g	0	1	1	0	0	1	1	0	0x66
1’s = 0	a, b, c, d, e, f	1	0	1	1	1	1	1	1	0xBF

Part (c) is a single-loop application of Kirchhoff’s voltage law. When a segment is lit, the current leaves the 5 V rail, passes through the saturated PNP digit driver, then through the LED, then through $R_2$, and finally into the open-collector inverter output transistor, which is itself saturated.

The series path carrying one segment current. Everything not dropped across the three fixed elements appears across R2.

Apply KVL to the segment loop (part c). Summing the drops around the loop,$$V_{source}=V_{CE(sat)}+V_F+I_{LED}R_2+V_{OL}$$so that$$R_2=\frac{V_{source}-V_{CE(sat)}-V_F-V_{OL}}{I_{LED}}=\frac{5.0-0.3-2.0-0.4}{10\times10^{-3}}=\frac{2.3}{0.010}$$
Evaluate and choose a preferred value. The calculation gives$$\boxed{R_2=230\ \Omega\ \text{(per segment; nearest E24 value }240\ \Omega)}$$A 240 Ω resistor yields $2.3/240=9.58$ mA, comfortably under the 10 mA ceiling, whereas 220 Ω would give 10.45 mA and exceed it. Seven such resistors are needed, one per segment line, and they are correctly placed in the shared segment lines rather than in the two common-anode leads — a single resistor in the anode lead would make each segment’s brightness depend on how many other segments happen to be lit.
Sanity-check the digit driver. The worst case for a digit-select transistor is all seven segments lit, i.e. $7\times10=70$ mA of collector current, so T0 and T1 must be chosen and base-driven for that, not for 10 mA. With a 5.1 kΩ base resistor and roughly 4.3 V across it the base current is about 0.84 mA, requiring a forced gain of about 83 — achievable with a small-signal PNP but worth verifying against the device’s saturation characteristics.

Check: the inverter output-LOW drop. The question gives $V_{CE(sat)}$ for the digit transistor and the LED drop, but not $V_{OL}$ for the open-collector inverter. The standard TTL guarantee of 0.4 V at rated sink current is used here, giving $R_2=230\ \Omega$. If the inverter drop is instead neglected (a common exam simplification), the same KVL gives $R_2=2.7/0.010=270\ \Omega$. Both are defensible provided the assumption is stated, as the paper’s own instructions invite; the 230 Ω result is the conservative one because it accounts for a real drop that would otherwise reduce the current below target.

Question 5 — final results
Part	Quantity	Result
(a)	Port B for the 10’s digit (4)	0110 0110₂ = 0x66 ($PB_7=0$)
(a)	Port B for the 1’s digit (0)	1011 1111₂ = 0xBF ($PB_7=1$)
(b)	Firmware	Set Port B to output; refresh loop: 0x66 → delay → blank → 0xBF → delay, repeated at ≥ 50 Hz (5 ms per digit at 100 Hz)
(c)	Segment resistor	$R_2=230\ \Omega$ (use 240 Ω, giving 9.58 mA)
(c)	Worst-case digit-driver current	70 mA (seven segments)

Topic. Port-driven multiplexed LED displays and current limiting.

Key relations. KVL around the segment loop, $R=\left(V_{source}-V_{CE(sat)}-V_F-V_{OL}\right)/I$; duty cycle $=1/N_{digits}$; refresh period $T=1/f_{refresh}$ with digit time $T/N_{digits}$; average LED current $=I_{peak}\times$ duty cycle.

Why this works. Multiplexing exists to save pins and parts. Two independent digits would need fourteen segment drivers; sharing the segment lines and switching the common anodes reduces that to seven drivers plus one select line, and the technique scales — a four-digit display still needs only seven segment drivers and four selects. The price is paid in average brightness and in software, which must refresh continuously. An LED needs an external current limit because its forward characteristic is exponential: a small increase in applied voltage produces a large increase in current, so a voltage source alone cannot set the operating point. The series resistor makes the current depend on a well-controlled voltage difference divided by a stable resistance instead.

Common pitfall. Forgetting the two transistor saturation drops and computing $R=(5-2)/0.01=300\ \Omega$, which under-drives every segment. The other classic error is placing one resistor in the common-anode lead instead of one per segment, which makes brightness vary with the digit being shown.

Source. Mazidi, McKinlay & Causey, PIC Microcontroller and Embedded Systems, Ch. 12 (LED and seven-segment interfacing); Mano & Ciletti, Digital Design 6th ed., §4.10 (seven-segment decoders).

← Question 4 Next: Question 6 →

Quantity	Symbol	Value
Supply	\(V_{source}\)	5.0 V
PNP digit-driver saturation voltage	\(V_{CE(sat)}\)	0.3 V
LED forward drop when lit	\(V_F\)	2.0 V
Open-collector TTL inverter output-LOW voltage	\(V_{OL}\)	0.4 V (standard TTL guarantee)
Target segment current	\(I_{LED}\)	10 mA
Digit select	\(PB_7\)	LOW turns on T1 (10’s digit); HIGH turns on T0 through the inverter (1’s digit)
Segment lines	\(PB_6\ldots PB_0\)	\(PB_6=g\), \(PB_5=f\), …, \(PB_0=a\)

Part	Quantity	Result
(a)	Port B for the 10’s digit (4)	0110 0110₂ = 0x66 (\(PB_7=0\))
(a)	Port B for the 1’s digit (0)	1011 1111₂ = 0xBF (\(PB_7=1\))
(b)	Firmware	Set Port B to output; refresh loop: 0x66 → delay → blank → 0xBF → delay, repeated at ≥ 50 Hz (5 ms per digit at 100 Hz)
(c)	Segment resistor	\(R_2=230\ \Omega\) (use 240 Ω, giving 9.58 mA)
(c)	Worst-case digit-driver current	70 mA (seven segments)