22-Elec-A4 Digital Systems and Computers · May 2015

Question 6 of 6: Big-endian storage and stack operation

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams, May 2015 — 07-Elec-A4 Digital Systems & Computers. Three hours, closed book, one approved Casio or Sharp calculator. Six questions are printed and five constitute a complete exam; every question is worth 12 marks, with the per-part split printed in the marking scheme on page 1. A flip-flop excitation table and a Boolean-identity sheet are attached to the paper. All six questions are solved below, so that the set works as a complete study resource.

Reference texts.

M. M. Mano and M. D. Ciletti, Digital Design, 5th ed. — Ch. 2 (Boolean algebra and gate-level minimisation), Ch. 3 (K-maps, NAND/NOR implementation), Ch. 4 (combinational design: adders and subtractors), Ch. 5 (synchronous sequential logic, state tables and diagrams, Moore vs Mealy).
J. F. Wakerly, Digital Design: Principles and Practices, 4th ed. — Ch. 4 (combinational design practices, bubble-to-bubble logic), Ch. 7 (latches, flip-flops and their excitation tables).
C. Hamacher, Z. Vranesic, S. Zaky and N. Manjikian, Computer Organization and Embedded Systems, 6th ed. — Ch. 2 (byte order, stacks), Ch. 3 (I/O, interrupt-driven serial transfer).
Freescale/Motorola, M68HC11 Reference Manual (rev. 6) — stack operation of PSHX/PSHY, big-endian storage of 16-bit operands, SCI registers.
TIA/EIA-232-F, Interface Between Data Terminal Equipment and Data Circuit-Terminating Equipment Employing Serial Binary Data Interchange — signal-level definitions used in Question 5(b).

Question 6 (12 marks) — Big-endian storage and stack operation

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A big-endian Motorola-style processor with byte-addressable memory; the 16-bit datum $\mathtt{10B2}_{16}$ to be stored at address $\mathtt{C109}_{16}$; the 16-bit datum $\mathtt{2EA4}_{16}$ to be pushed with the stack pointer holding $\mathtt{DFE8}_{16}$ before the push; and two three-byte memory windows, drawn with low memory at the top.

Find. (a) the byte contents of $\mathtt{C108}_{16}$–$\mathtt{C10A}_{16}$ after the store; (b) the byte contents of $\mathtt{DFE7}_{16}$–$\mathtt{DFE9}_{16}$ after the push; (c) the value of SP after the push.

Approach. Apply the big-endian rule — most significant byte at the lowest address — to the store, then apply the Motorola stack convention in which SP points at the next free byte and is post-decremented after each byte is written, taking care that the resulting pair of bytes must still read big-endian in memory.

(a) Split the datum. $\mathtt{10B2}_{16}$ has high-order byte $\mathtt{10}_{16}$ and low-order byte $\mathtt{B2}_{16}$. Big-endian means the big end of the number goes to the first (lowest) address, so $\boxed{(\mathtt{C109}_{16})=\mathtt{10}_{16}\ \text{and}\ (\mathtt{C10A}_{16})=\mathtt{B2}_{16}}$. The instruction names $\mathtt{C109}_{16}$ as the operand address, and a 16-bit store occupies that address and the one above it; $\mathtt{C108}_{16}$ lies below the operand address and is therefore untouched. Its previous contents remain whatever they were.

Question 6(a) — result of the 16-bit store. The high-order byte takes the lower address.

(b) Apply the Motorola push convention. On the 6800/68HC11 family the stack grows towards lower addresses and SP points at the next free byte, so each push writes at $(\text{SP})$ and then decrements SP. A 16-bit push writes the low-order byte first: $\mathtt{A4}_{16}\to\mathtt{DFE8}_{16}$, SP becomes $\mathtt{DFE7}_{16}$; then the high-order byte $\mathtt{2E}_{16}\to\mathtt{DFE7}_{16}$, SP becomes $\mathtt{DFE6}_{16}$. Hence $\boxed{(\mathtt{DFE7}_{16})=\mathtt{2E}_{16}\ \text{and}\ (\mathtt{DFE8}_{16})=\mathtt{A4}_{16}}$, with $\mathtt{DFE9}_{16}$ unchanged.
Cross-check the byte order against part (a). The pair now in memory reads $\mathtt{2E}$ at the lower address and $\mathtt{A4}$ at the higher one, i.e. $\mathtt{2EA4}_{16}$ read big-endian — exactly the same convention as the store in part (a). This is the whole reason the low byte is pushed first on a downward-growing stack: writing the high byte first would leave the word stored little-endian and the matching PULL would return the bytes swapped.

Question 6(b) — result of the 16-bit push. Two bytes are written below and at the original SP; the word still reads big-endian in memory.

(c) Final stack pointer. Two bytes were pushed and SP is decremented once per byte, so $$\text{SP}_{\text{after}}=\mathtt{DFE8}_{16}-2=\boxed{\mathtt{DFE6}_{16}}$$ which again points at the next free byte, one location below the high-order byte just written.

Question 6 — final results
Location	Contents after execution
$\mathtt{C108}_{16}$	unchanged (below the operand address)
$\mathtt{C109}_{16}$	$\mathtt{10}_{16}$ (high-order byte)
$\mathtt{C10A}_{16}$	$\mathtt{B2}_{16}$ (low-order byte)
$\mathtt{DFE7}_{16}$	$\mathtt{2E}_{16}$ (high-order byte)
$\mathtt{DFE8}_{16}$	$\mathtt{A4}_{16}$ (low-order byte)
$\mathtt{DFE9}_{16}$	unchanged
SP after PUSH	$\mathtt{DFE6}_{16}$

Topic. Byte ordering of multi-byte operands and the mechanics of a descending, next-free-byte stack.

Key relations. Big-endian: $(\text{addr})=$ MS byte, $(\text{addr}+1)=$ LS byte. Motorola push of $n$ bytes: write at $(\text{SP})$ then $\text{SP}\leftarrow\text{SP}-1$, repeated, so $\text{SP}_{\text{after}}=\text{SP}_{\text{before}}-n$. Pull is the exact reverse: $\text{SP}\leftarrow\text{SP}+1$ then read.

Why this works. Endianness is a convention about which end of a number is placed at the lower address, and nothing more — the bits inside each byte are unaffected. Big-endian has the practical advantage that a memory dump reads left-to-right in the same order a person writes the number, which is why it dominates Motorola architectures and network protocol headers. On the stack, the combination “grows downward” plus “low byte pushed first” is not two independent choices: it is the only pairing that leaves the pushed word readable in the machine's own big-endian order, so that a 16-bit read at the new SP+1 recovers it directly.

Common pitfall. Placing $\mathtt{B2}_{16}$ at $\mathtt{C109}_{16}$, which is the little-endian (Intel) answer the question is explicitly steering away from. The second pitfall is treating SP as pointing at the last used byte rather than the next free one; on that convention the bytes would land at $\mathtt{DFE7}_{16}$ and $\mathtt{DFE6}_{16}$ and SP would finish at $\mathtt{DFE6}_{16}$ — the same final SP but the wrong memory picture, which is why the exam supplies the “SP before PUSH” marker on the diagram. The third is decrementing SP only once for a 16-bit push.

Source. Hamacher, Vranesic, Zaky & Manjikian, Computer Organization and Embedded Systems, 6th ed., §2.2 (memory locations, byte addressability, big-endian and little-endian assignment) and §2.8 (stacks and subroutine linkage); Freescale, M68HC11 Reference Manual, §6 (instruction set: PSHX/PSHY/PULX stack behaviour and SP conventions).

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