22-Elec-A4 Digital Systems and Computers · December 2017
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
National Exams — 16-Elec-A4 Digital Systems & Computers — December 2017. Closed book; 3 hours; six questions of 12 marks each, of which any five constitute a complete paper. All six are solved below as a study resource. Permitted aids: Casio or Sharp approved calculator; a sheet of Boolean identities and a flip-flop excitation table are supplied with the paper.
Reference texts. M. Morris Mano & M. D. Ciletti, Digital Design (Pearson); C. H. Roth & L. L. Kinney, Fundamentals of Logic Design (Cengage); J. F. Wakerly, Digital Design: Principles and Practices (Pearson); Hamacher, Vranesic & Zaky, Computer Organization (McGraw-Hill) for the interrupt / timer material.
Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.
Approach. This is a descriptive computer-organisation question; the answer is given as flowing prose organised by the six sub-parts, drawing on the standard microcontroller timer subsystem (e.g. the M68HC11 family used in the course) and the interrupt mechanism.
(i) Input Capture. An input-capture channel latches the current value of the free-running timer counter into a capture register at the instant a selected edge (rising, falling, or either) appears on an input pin, and it can raise a flag/interrupt. Its applications are all forms of measuring time or events referenced to the outside world: measuring the period or frequency of an incoming signal, measuring pulse width or duty cycle, time-stamping external events, tachometry / speed sensing from a shaft encoder, and phase or time-of-arrival measurement. Because the capture is done in hardware, the recorded time is accurate to the timer clock regardless of software latency.
(ii) Output Compare. An output-compare channel continuously compares the free-running counter against a programmed value and, on a match, performs a hardware action on an output pin (set, clear, toggle) and/or raises a flag/interrupt. Its applications are all forms of generating precise time intervals and waveforms: producing accurate delays, generating single pulses of a defined width, square waves and pulse-width-modulated (PWM) signals for motor or lamp control, periodic interrupts for a real-time software tick, and stepper-motor or general timing sequences. Again the pin action is taken by hardware at the exact count, independent of instruction timing.
(iii) The time base. The time base is a free-running binary counter driven from the system clock through a programmable prescaler. The counter increments continuously (typically a 16-bit counter that rolls over and sets a timer-overflow flag), so its instantaneous value is a running measure of elapsed time; the prescaler sets the resolution (time per count) and hence the maximum interval before roll-over. Input-capture and output-compare both work against this one shared counter, and software extends the range by counting the overflow interrupts.
(i) Main components. Implementing interrupts requires: an interrupt request line (or lines) from each source (here the timer flags); logic in the peripheral to set an interrupt flag and an interrupt-enable bit that gates it; a global interrupt mask/enable bit in the processor’s condition-code (status) register; priority-resolution logic when several sources can request at once; and an interrupt-vector mechanism — a table in memory that supplies the starting address of the service routine for each source.
(ii) Sequence of steps. On an enabled request the processor: (1) finishes the instruction currently executing; (2) tests the request against the global mask and any priority; (3) automatically saves the machine context — it pushes the program counter (and, on the 68HC11, the CPU registers A, B, X, Y and the condition-code register) onto the stack; (4) sets the interrupt mask to block further interrupts of equal/lower priority; (5) fetches the service-routine address from the corresponding interrupt vector and loads it into the program counter; (6) executes the interrupt service routine, which clears the peripheral’s flag and does the required work; and (7) executes a return-from-interrupt (RTI) instruction that pops the saved context off the stack, restoring the registers and the program counter so the interrupted program resumes exactly where it left off.
(iii) Registers most involved. The program counter (PC) — saved and reloaded from the vector; the stack pointer (SP) — which addresses the save/restore area in memory; the condition-code / status register (CCR) — which holds the global interrupt-mask (I) bit and is itself saved and restored; and the general working registers (accumulators and index registers) that are stacked so the service routine cannot corrupt the interrupted program’s state.
