22-Elec-A4 Digital Systems and Computers · December 2018
Question 2 of 6: Synchronous counter with JK flip-flops
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
22-Elec-A4 Digital Systems & Computers — 2018-Dec (Worked Solutions)
National Exams — December 2018 · 16-Elec-A4 Digital Systems & Computers. Closed book, 3 hours. Six questions, 12 marks each; the rubric requires any five, but all six are solved here as a study resource. Approved Casio/Sharp calculator permitted. A Boolean-identity table and the flip-flop excitation table are supplied with the paper and are used where needed.
Reference texts. M. M. Mano & M. D. Ciletti, Digital Design (6th ed.) — Boolean minimization, NAND/NOR realizations, K-maps, synchronous counters; J. F. Wakerly, Digital Design: Principles and Practices (5th ed.) — counters, PAL/PLA devices; C. Hamacher, Z. Vranesic, S. Zaky & N. Manjikian, Computer Organization and Embedded Systems (6th ed.) — CPU registers, endianness, stacks, parallel I/O; Motorola M68HC11 Reference Manual — big-endian storage, PUSH semantics, Port B addressing.
Question 2: Synchronous counter with JK flip-flops (12 marks)
Given. The 6-state Gray-like sequence on $Q_AQ_BQ_C$ (A = MSB, C = LSB); JK flip-flops; the standard excitation table $0\!\to\!0:JK{=}0X$, $0\!\to\!1:1X$, $1\!\to\!0:X1$, $1\!\to\!1:X0$.
Find. The six JK input equations, a proof of self-start, and the output timing diagram.
Part (a): state-transition diagram of the required 6-state cycle. Unused states are 110 and 111.
Approach. Tabulate present→next for each used state, read the JK inputs from the excitation table, minimise each on a 3-variable K-map (with 110, 111 as don't-cares), then substitute the two unused states into the finished equations to test self-start.
The excitation table gives, for every transition, the flip-flop inputs:
State-transition table with JK inputs (X = don't-care)
$Q_A Q_B Q_C$
$Q_A^{+}Q_B^{+}Q_C^{+}$
$J_A K_A$
$J_B K_B$
$J_C K_C$
0 0 0
0 1 0
0 X
1 X
0 X
0 1 0
1 0 0
1 X
X 1
0 X
1 0 0
1 0 1
X 0
0 X
1 X
1 0 1
0 1 1
X 1
1 X
X 0
0 1 1
0 0 1
0 X
X 1
X 0
0 0 1
0 0 0
0 X
0 X
X 1
Minimise the A-stage inputs. $J_A$ is 1 only at 010 (with 110/111 as don't-cares) and $K_A$ is 1 at 101 and 011: $$J_A=B\overline{C},\qquad K_A=C.$$
Minimise the B-stage inputs. $J_B$ is 1 at 000 and 101; grouping with don't-cares gives $\overline{A}\,\overline{C}+AC$. Every entry of $K_B$ is 1 or don't-care, so it ties high: $$J_B=\overline{A}\,\overline{C}+AC=\overline{A\oplus C},\qquad K_B=1.$$
Minimise the C-stage inputs. $J_C$ is 1 only at 100 (expands to $A$ using the don't-cares) and $K_C$ is 1 only at 001 (expands to $\overline{A}\,\overline{B}$): $$\boxed{J_C=A,\qquad K_C=\overline{A}\,\overline{B}.}$$
Draw the circuit. Three JK flip-flops clocked in parallel, each driven by the equations above (a single 2-input AND for $J_A$, an XNOR for $J_B$, one AND for $K_C$; $K_B$ tied to logic 1).
Part (a): final synchronous counter. Each J/K pin carries its minimised expression; all flip-flops share CLK and $\overline{CLR}$.
(b) Self-start test. Substituting the unused states into the finished equations: 110 gives $J_AK_A{=}10,\ J_BK_B{=}01,\ J_CK_C{=}10\Rightarrow 101$, and 111 gives $J_AK_A{=}01,\ J_BK_B{=}11,\ J_CK_C{=}10\Rightarrow 001$. Both unused states drop into the main cycle in one clock, so the counter is $\boxed{\text{self-starting}}$.
Part (b): both unused states enter the cycle after a single clock — the design is self-correcting.
(c) Timing diagram. Starting from 000 at $t=0$ (after $\overline{CLR}$ is released) the outputs step through 000, 010, 100, 101, 011, 001 and repeat.
Part (c): output waveforms over 8 clock pulses; the pattern repeats every 6 clocks.
