22-Elec-A4 Digital Systems and Computers · December 2018
Question 5 of 6: Big-endian storage and the stack
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
22-Elec-A4 Digital Systems & Computers — 2018-Dec (Worked Solutions)
National Exams — December 2018 · 16-Elec-A4 Digital Systems & Computers. Closed book, 3 hours. Six questions, 12 marks each; the rubric requires any five, but all six are solved here as a study resource. Approved Casio/Sharp calculator permitted. A Boolean-identity table and the flip-flop excitation table are supplied with the paper and are used where needed.
Reference texts. M. M. Mano & M. D. Ciletti, Digital Design (6th ed.) — Boolean minimization, NAND/NOR realizations, K-maps, synchronous counters; J. F. Wakerly, Digital Design: Principles and Practices (5th ed.) — counters, PAL/PLA devices; C. Hamacher, Z. Vranesic, S. Zaky & N. Manjikian, Computer Organization and Embedded Systems (6th ed.) — CPU registers, endianness, stacks, parallel I/O; Motorola M68HC11 Reference Manual — big-endian storage, PUSH semantics, Port B addressing.
Question 5: Big-endian storage and the stack (12 marks)
Given. Big-endian (Motorola) byte order; a 16-bit value 0x7A01 (high byte 0x7A, low byte 0x01); target address 0xC239; stack pointer SP = 0xDC51 pointing at the next free byte.
Find. The bytes placed in memory for the store and the push, and the post-push value of SP.
Approach. Big-endian places the most-significant byte at the lowest address. A Motorola PUSH writes the low byte at the current SP, decrements, writes the high byte, and decrements again, so the two bytes still end up big-endian in memory with SP left below them.
(a) Store 0x7A01 → 0xC239. High byte first at the low address: address 0xC239 receives 0x7A and 0xC23A receives 0x01; 0xC238 is untouched.
Part (a): big-endian store — high byte 0x7A at 0xC239, low byte 0x01 at 0xC23A.
(b) Push 0x7A01 with SP = 0xDC51. The PUSH stacks the low byte first: $[\text{0xDC51}]\leftarrow$ 0x01, then SP decrements and $[\text{0xDC50}]\leftarrow$ 0x7A. In memory the high byte 0x7A sits at the lower address 0xDC50 — big-endian, consistent with part (a).
Part (b): after the push, 0xDC50 = 0x7A (high) and 0xDC51 = 0x01 (low).
(c) Stack pointer after PUSH. Two bytes were pushed, so SP decrements twice from 0xDC51: $$\text{SP}=\text{0xDC51}-2=\boxed{\mathtt{DC4F}_{16}}.$$ It again points at the next free (lower) byte, below the value just stored.