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22-Elec-A5 Electronics · December 2017

Question 1 of 5: Common-Gate MOSFET Amplifier

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

National Exams — December 2017 · 16-Elec-A5, Electronics. Closed-book, 3 hours. Answer all FIVE (5) questions; each worth 20 marks. Unless stated, op-amps are ideal and supply rails are ±15 V.

Reference texts: A. S. Sedra & K. C. Smith, Microelectronic Circuits, 7th ed. (Oxford) — Ch. 4 (diode circuits & rectifiers), Ch. 5–7 (MOSFET and BJT amplifiers, biasing and small-signal models), Ch. 2 & 9 (ideal op-amps, closed-loop bandwidth and slew rate). Cross-reference: R. C. Jaeger & T. N. Blalock, Microelectronic Circuit Design.

Question 1: Common-Gate MOSFET Amplifier (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. The single MOSFET and its bias/coupling network:

Given data — Question 1
QuantityValueQuantityValue
$V_{TH}$1 V$V_{CC}$10 V
$K$ (transconductance param.)1 mA/V$^2$$I_{bias}$2 mA
$\lambda$0.1 V$^{-1}$$R_1,\,R_2$10 kΩ, 5 kΩ
$R_D$2 kΩ$C_1,C_2$$\infty$ (AC short)

Find. The small-signal voltage gain $A_v=v_o/v_{in}$, the input resistance $R_{in}$ seen looking into the source, and the output resistance $R_o$ seen looking into the drain.

[Figure not reproduced: Q1: common-gate MOSFET amplifier (redrawn from exam). Gate AC-grounded by R1/R2, input at source through C1, output at drain through C2. See the official exam paper or the cited reference text.]

Q1: common-gate MOSFET amplifier (redrawn from exam). Gate AC-grounded by R1/R2, input at source through C1, output at drain through C2.

Approach. Recognise the topology (input at the source, output at the drain, gate held at AC ground) as a common-gate stage; fix the operating point from the source current source, evaluate $g_m$ and $r_o$, then apply the common-gate small-signal relations.

  1. Identify the configuration. Although the header says “common base,” $M_1$ is a MOSFET whose gate is tied through the $R_1/R_2$ divider (a DC bias point that is an AC ground), whose source receives $v_{in}$ through $C_1$, and whose drain delivers $v_o$ through $C_2$. This is a common-gate amplifier — non-inverting, with low input resistance and moderate gain. The body is tied to the source, so there is no body effect ($g_{mb}=0$).
  2. Set the operating point. The ideal current source in the source lead fixes the drain current directly: $I_D=I_{bias}=2\text{ mA}$. From the saturation law (neglecting the small $(1+\lambda v_{DS})$ correction in the overdrive), the overdrive is $$V_{ov}=v_{GS}-V_{TH}=\sqrt{\frac{2I_D}{K}}=\sqrt{\frac{2(2\text{ mA})}{1\text{ mA/V}^2}}=2\text{ V}.$$ A DC check confirms saturation: $V_D=V_{CC}-I_D R_D=10-(2\text{ mA})(2\text{ k}\Omega)=6\text{ V}$ and $V_G=V_{CC}\,R_2/(R_1+R_2)=3.33\text{ V}$, so $V_{DS}\gt 0$ and the device is in saturation.
  3. Compute the small-signal parameters. The transconductance and output resistance at this bias are $$g_m=\sqrt{2KI_D}=K\,V_{ov}=(1\text{ mA/V}^2)(2\text{ V})=2\text{ mA/V},\qquad r_o=\frac{1}{\lambda I_D}=\frac{1}{(0.1)(2\text{ mA})}=5\text{ k}\Omega .$$
  4. Small-signal gain. With the gate grounded, $v_{gs}=-v_{in}$. Writing KCL at the drain node (load $R_D$ to AC ground, $r_o$ from drain to source) gives the exact common-gate result $$A_v=\frac{v_o}{v_{in}}=\frac{(1+g_m r_o)\,R_D}{R_D+r_o} =\frac{\bigl(1+(2\text{ mA/V})(5\text{ k}\Omega)\bigr)(2\text{ k}\Omega)}{2\text{ k}\Omega+5\text{ k}\Omega} =\frac{11(2\text{ k}\Omega)}{7\text{ k}\Omega}.$$ $$\boxed{A_v=+3.14\ \text{V/V}}$$ The result is positive: a common-gate stage is non-inverting. (Neglecting $r_o$ would give the textbook $g_m R_D=4$; the finite $r_o=5\text{ k}\Omega$, comparable to $R_D$, pulls it down to 3.14.)
  5. Input resistance (looking into the source). The source terminal, loaded at the drain by $R_D$, presents $$R_{in}=\frac{R_D+r_o}{1+g_m r_o}=\frac{2\text{ k}\Omega+5\text{ k}\Omega}{11}=636\ \Omega\;\approx\;\frac{1}{g_m}=500\ \Omega .$$ The low input resistance ($\approx 1/g_m$) is the defining trait of the common-gate stage.
  6. Output resistance (looking into the drain). With the input driven by an ideal source ($R_{sig}=0$), the source node is AC-grounded, $v_{gs}=0$, the controlled source is off, and only $r_o$ and $R_D$ remain in parallel: $$R_o=R_D\parallel r_o=\frac{(2\text{ k}\Omega)(5\text{ k}\Omega)}{2\text{ k}\Omega+5\text{ k}\Omega}=1.43\text{ k}\Omega .$$
Final results — Question 1
QuantitySymbolValue
Transconductance$g_m$2 mA/V
Output resistance of device$r_o$5 kΩ
Small-signal voltage gain$v_o/v_{in}$+3.14 V/V
Input resistance (at source)$R_{in}$636 Ω
Output resistance (at drain)$R_o$1.43 kΩ
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