Question 4 of 5: Common-Source Amplifier — Bias Design and Gain

Question 4: Common-Source Amplifier — Bias Design and Gain (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Single-stage CS amplifier, $V_{TH}=1\text{ V}$, $K=4\text{ mA/V}^2$, $\lambda=0$ ($r_o\to\infty$). Design targets: $V_{DD}=15\text{ V}$, $I_D=0.5\text{ mA}$, $V_S=3.5\text{ V}$, $V_D=6\text{ V}$. For part (b): $R_{in}=1.67\text{ M}\Omega$ ($=R_{G1}\parallel R_{G2}$), source resistance $R_1=100\text{ k}\Omega$, load $R_L=200\text{ k}\Omega$.

Find. (a) $R_{G1},R_{G2},R_S,R_D$; (b) overall gain $v_{out}/v_1$.

Approach. Size $R_S$ and $R_D$ from the target node currents/voltages, find $V_{GS}$ from the square law to fix the gate DC level, split the gate divider to give that level and the required $R_{in}$; then compute the degenerated gain (the source resistor is not bypassed) and fold in the input divider and output loading.

1. Source and drain resistors (part a). Directly from the target currents, $$R_S=\frac{V_S}{I_D}=\frac{3.5\text{ V}}{0.5\text{ mA}}=7\text{ k}\Omega,\qquad R_D=\frac{V_{DD}-V_D}{I_D}=\frac{15-6}{0.5\text{ mA}}=18\text{ k}\Omega.$$
2. Gate DC level. From the square law ($\lambda=0$), the overdrive is $$V_{ov}=\sqrt{\frac{2I_D}{K}}=\sqrt{\frac{2(0.5\text{ mA})}{4\text{ mA/V}^2}}=0.5\text{ V}\;\Rightarrow\;V_{GS}=1.5\text{ V},$$ so the gate must sit at $V_G=V_{GS}+V_S=1.5+3.5=5\text{ V}$.
3. Gate divider. The divider must both set $V_G=5\text{ V}$ and present $R_{in}=R_{G1}\parallel R_{G2}=1.67\text{ M}\Omega$: $$\frac{R_{G2}}{R_{G1}+R_{G2}}=\frac{V_G}{V_{DD}}=\frac{5}{15}=\frac13\;\Rightarrow\;R_{G1}=2R_{G2},\qquad R_{G1}\parallel R_{G2}=\tfrac23 R_{G2}=1.67\text{ M}\Omega.$$ Solving, $R_{G2}=2.5\text{ M}\Omega$ and $R_{G1}=5\text{ M}\Omega$ (check: $5\parallel 2.5=1.67\text{ M}\Omega$ and $15\cdot\tfrac{2.5}{7.5}=5\text{ V}$). $$\boxed{R_{G1}=5\text{ M}\Omega,\;R_{G2}=2.5\text{ M}\Omega,\;R_S=7\text{ k}\Omega,\;R_D=18\text{ k}\Omega}$$
4. Small-signal transconductance (part b). $g_m=\sqrt{2KI_D}=K\,V_{ov}=(4\text{ mA/V}^2)(0.5\text{ V})=2\text{ mA/V}$; with $\lambda=0$, $r_o=\infty$.
5. Degenerated stage gain. The schematic shows no bypass capacitor across $R_S$, so the source is degenerated. With the drain loaded by $R_D\parallel R_L$, $$\frac{v_{out}}{v_{g}}=-\frac{g_m(R_D\parallel R_L)}{1+g_m R_S},\quad R_D\parallel R_L=18\text{ k}\parallel 200\text{ k}=16.5\text{ k}\Omega,$$ $$\frac{v_{out}}{v_g}=-\frac{(2\text{ mA/V})(16.5\text{ k}\Omega)}{1+(2\text{ mA/V})(7\text{ k}\Omega)}=-\frac{33.0}{15}=-2.20.$$
6. Input attenuation and overall gain. The source $v_1$ drives the gate node through $R_1$ into $R_{in}$ ($C_1$ couples the signal to the gate), giving a divider $$\frac{v_g}{v_1}=\frac{R_{in}}{R_1+R_{in}}=\frac{1.67\text{ M}\Omega}{0.1\text{ M}\Omega+1.67\text{ M}\Omega}=0.943.$$ Therefore the overall gain is $$\frac{v_{out}}{v_1}=0.943\times(-2.20)=\boxed{-2.08\ \text{V/V}.}$$