Question 1 of 8: Transistor Amplifier — Bias Design and Load Lines

Question 1: Transistor Amplifier — Bias Design and Load Lines (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A single-stage common-emitter amplifier with voltage-divider bias, an emitter bypass capacitor and a capacitively coupled load, with the component values listed below.

Find. The bias resistors $R_E$ and $R_C$ that place the quiescent point at $I_C = 2$ mA and $V_{CE} = 6$ V, the dc and ac load lines on the output characteristics, and the peak output voltage produced by the given signal current.

Approach. Replace the base divider by its Thévenin equivalent to fix the base potential, walk KVL down the base–emitter loop for $R_E$ and along the collector–emitter loop for $R_C$, then draw the two load lines — the dc line set by $R_C + R_E$ and the ac line set by $R_C \parallel R_L$ through the quiescent point.

1. Fix the base potential from the divider. With negligible base loading the divider acts as an unloaded potentiometer, so $$V_B = V_{CC}\,\frac{R_1}{R_1+R_2} = 15 \times \frac{10}{10+30} = 3.75\ \text{V}.$$ The assumption is worth checking: the Thévenin resistance is $R_1 \parallel R_2 = 7.5\ \text{k}\Omega$ and the base current is only $I_B = I_C/\beta = 20\ \mu\text{A}$, so the drop it causes is $20\ \mu\text{A} \times 7.5\ \text{k}\Omega = 0.15\ \text{V}$, about 4 % of $V_B$. The divider is stiff enough for the standard design equations.
2. Convert collector current to emitter current. The emitter carries both the collector and base currents, so $$I_E = I_C\,\frac{\beta+1}{\beta} = 2\ \text{mA} \times \frac{101}{100} = 2.02\ \text{mA}.$$
3. Solve the base–emitter loop for $R_E$. Subtracting the base–emitter drop from the base potential leaves the emitter potential $V_E = V_B - V_{BE} = 3.75 - 0.7 = 3.05\ \text{V}$, and this appears across $R_E$: $$R_E = \frac{V_E}{I_E} = \frac{3.05}{2.02\times 10^{-3}} = \boxed{1.51\ \text{k}\Omega}$$
4. Solve the collector–emitter loop for $R_C$. The collector sits $V_{CE}$ above the emitter, $V_C = V_E + V_{CE} = 3.05 + 6 = 9.05\ \text{V}$, and the remainder of the supply is dropped across $R_C$: $$R_C = \frac{V_{CC}-V_C}{I_C} = \frac{15-9.05}{2\times 10^{-3}} = \boxed{2.98\ \text{k}\Omega}$$ Nearest standard 5 % values would be 1.5 k$\Omega$ and 3.0 k$\Omega$, which shift the operating point by well under a tenth of a volt.
5. Draw the dc load line. For direct current both $R_C$ and $R_E$ are in the collector–emitter path, so $$V_{CE} = V_{CC} - I_C\,(R_C+R_E).$$ The line runs between the open-circuit intercept $V_{CE} = 15\ \text{V}$ at $I_C = 0$ and the saturation intercept $I_C = 15/(2975+1510) = 3.34\ \text{mA}$ at $V_{CE} = 0$, passing through the quiescent point $(6\ \text{V},\ 2\ \text{mA})$ as designed.
6. Draw the ac load line. At signal frequencies the bypass capacitor shorts $R_E$ and the coupling capacitor connects $R_L$ in parallel with $R_C$, so the collector works into $$r_{ac} = R_C \parallel R_L = \frac{2975 \times 3000}{2975+3000} = 1.494\ \text{k}\Omega.$$ The ac line is steeper than the dc line and must pass through the same quiescent point, giving intercepts $V_{CE} = 6 + (2\ \text{mA})(1.494\ \text{k}\Omega) = 8.99\ \text{V}$ and $I_C = 2 + 6/1.494 = 6.02\ \text{mA}$.
7. Estimate the output voltage. The signal collector current is $\beta$ times the signal base current, $i_c = \beta\, i_b = 100 \times 10\ \mu\text{A} = 1\ \text{mA}$ peak, and it develops the output across the ac load: $$v_o = i_c \, r_{ac} = (1\times10^{-3})(1494) = \boxed{1.49\ \text{V peak}}$$ that is $2.99\ \text{V}$ peak-to-peak, or $1.06\ \text{V rms}$, inverted with respect to the input.
8. Confirm the swing is not clipped. Travelling up the ac load line the transistor reaches cut-off after $I_C\,r_{ac} = 2.99\ \text{V}$, and travelling down it reaches saturation after $V_{CE} = 6\ \text{V}$. The required 1.49 V peak fits inside both limits, so the stage is operating linearly — though the positive half-cycle has only twice the headroom it needs, which is the practical limit on this bias point.