Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
17-Phys-A5-B — Analog and Digital Electronic Circuits — National Exams, December 2018
3 hours duration. Open book exam. Answer all SIX (6) questions.
Reference texts: A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. (BJT/MOSFET biasing and small-signal amplifiers Ch. 6–7, current-mirror loads and cascodes Ch. 7–8, feedback amplifiers Ch. 10, high-frequency response and open-circuit time constants Ch. 9, D/A converters Ch. 17); M. M. Mano & M. D. Ciletti, Digital Design, 6th ed. (Boolean algebra Ch. 2, static CMOS logic gates Ch. 10).
$M_1$ (PMOS, source at $V_{DD}$, gate driven through $R_{sig}$ by $v_{sig}$) is loaded by an NMOS current mirror: $M_b$ (diode-connected, sets the mirror reference from $I_{bias}$) and $M_2$ (mirrors the current, drain tied to $M_1$'s drain at $v_O$).
[Figure not reproduced: Fig. 3 from the exam paper. See the official exam paper or the cited reference text.]
Fig. 3 (reproduced from the exam paper) — PMOS common-source amplifier ($M_1$) with an NMOS current-mirror active load ($M_b$, $M_2$).
Approach. (a)/(b) read the topology and mirror action; (c) standard $-g_m R_{out}$ with $R_{out}=r_{o1}\|r_{o2}$; (d) sum the open-circuit time constants of all four capacitors.
(a) Identify the amplifier. $M_1$'s source is tied to $V_{DD}$ and its gate is driven (through $R_{sig}$) by $v_{sig}$, with the output taken at its drain: $M_1$ is a common-source amplifier. $M_b/M_2$ form an NMOS current-mirror active load in place of a passive drain resistor.
(b) Find $I_{D1}$. $M_b$ and $M_2$ share the same $(W/L)$ and process parameters, so the mirror copies the reference current exactly: $I_{D2}=I_{bias}=2\,\text{mA}$. At $v_O$ (the shared $M_1$/$M_2$ drain node, with $C_L$ open at DC) KCL gives $I_{D1}=I_{D2}$, so $$\boxed{I_{D1}=2.00\ \text{mA}}$$
Gain. $$\boxed{A_v=\frac{v_o}{v_{sig}}=-g_{m1}R_{out}=-(2\,\text{mA/V})(5\,\text{k}\Omega)=-10.0\ \text{V/V}}$$ (the gate draws no current, so $R_{sig}$ causes no midband attenuation).
(d) Open-circuit time constants. Four capacitors load the circuit: $C_{gs1}$ sees only $R_{sig}$; $C_{gd1}$ bridges gate to drain (Miller-type resistance); $M_2$'s gate is AC-grounded (fixed mirror bias, no signal path into it), so $C_{gd2}$ simply bridges $v_O$ to ground; $C_L$ also sits at $v_O$.
$$R_{C_{gs1}}=R_{sig}=10\,\text{k}\Omega \;\Rightarrow\; \tau_1=C_{gs}R_{sig}=0.50\,\text{ns}$$
$$R_{C_{gd1}}=R_{sig}\left(1+g_{m1}R_{out}\right)+R_{out}=10\text{k}(1+10)+5\text{k}=115\,\text{k}\Omega \;\Rightarrow\; \tau_2=C_{gd}R_{C_{gd1}}=2.30\,\text{ns}$$
$$\begin{aligned} R_{C_{gd2}}&=R_{out}=5\,\text{k}\Omega \;\Rightarrow\; \tau_3=C_{gd}R_{out}=0.10\,\text{ns} \\ R_{C_L}&=R_{out} \;\Rightarrow\; \tau_4=C_LR_{out}=0.25\,\text{ns} \end{aligned}$$
Sum and invert. $$\sum\tau=0.50+2.30+0.10+0.25=3.15\,\text{ns}$$ $$\boxed{f_H=\frac{1}{2\pi\sum\tau}=\frac{1}{2\pi(3.15\,\text{ns})}=50.5\ \text{MHz}}$$
Treating $M_2$'s gate as an AC ground is the standard exam-level simplification. Strictly, the mirror node sits at $1/g_{mb}\parallel r_{ob}=476\,\Omega$ (the diode-connected $M_b$). Including that resistance adds $C_{gs,b}+C_{gs2}=100\,\text{fF}$ at the mirror node ($\tau=0.048\,\text{ns}$; $C_{gd,b}$ is shorted by the diode connection) and raises $C_{gd2}$'s resistance to $R_g+R_{out}+g_{m2}R_gR_{out}=10.24\,\text{k}\Omega$ ($\tau=0.205\,\text{ns}$). Then $\sum\tau=3.30\,\text{ns}$ and $f_H\approx48.2\,\text{MHz}$, less than 5 % below the boxed estimate, so the simplification does not change the answer materially.
Quantity
Value
(a) Amplifier type
Common-source (PMOS $M_1$) with NMOS current-mirror load