17-Phys-A5, December 2018, Q6

Question 6 (15 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. NMOS pull-down network between $Y$ and $V_{SS}$: from $Y$, transistors $A$ and $B$ are in parallel down to a shared node $N_M$; from $N_M$ to $V_{SS}$, transistor $C$ is in parallel with the series pair $D$–$E$.

Find. (a) the dual PUN (PMOS) completing the static CMOS gate; (b) the Boolean function $Y$.

Fig. 6 — given PDN: $(A\parallel B)$ in series with $\bigl(C\parallel(D\text{ series }E)\bigr)$, between $Y$ and $V_{SS}$.

Approach. Read the PDN as nested series/parallel stages, write when it conducts, take the complement for $Y$, then build the PUN as the series–parallel dual of the PDN (same gate signals, PMOS devices).

Read the PDN's two stages. $Y\to N_M$ conducts when $A$ OR $B$ is on; $N_M\to V_{SS}$ conducts when $C$ is on, OR ($D$ AND $E$) are both on. The whole PDN conducts (pulling $Y$ low) when both stages conduct: $$\text{PDN}_{on}=(A+B)\cdot(C+DE)$$
Take the complement for $Y$. $$Y=\overline{(A+B)(C+DE)}$$
Build the dual PUN. Swap every series connection for parallel and every parallel for series, keeping the same gate signals but PMOS devices: since the PDN is $(A\parallel B)$ in series with $\bigl(C\parallel(D\cdot E)\bigr)$, the PUN is $$(A\text{ series }B)\ \parallel\ \Bigl(C\text{ series }(D\parallel E)\Bigr)$$ i.e. PMOS $A,B$ in series form one branch from $V_{DD}$ to $Y$; PMOS $C$ in series with (PMOS $D\parallel$ PMOS $E$) forms the second branch, the two branches in parallel.
Apply De Morgan to double-check against the PUN. $$Y=\overline{(A+B)}+\overline{(C+DE)}=\overline{A}\,\overline{B}+\overline{C}\,\overline{(DE)}=\boxed{\overline{A}\,\overline{B}+\overline{C}\left(\overline{D}+\overline{E}\right)}$$ This matches exactly what the constructed PUN conducts (PMOS $A$ AND $B$ both on when $A=B=0$, giving the $\overline{A}\,\overline{B}$ term; PMOS $C$ on AND (PMOS $D$ or $E$ on) giving the $\overline{C}(\overline{D}+\overline{E})$ term) — confirming the dual is correct.

Quantity	Result
PDN conduction condition	$(A+B)(C+DE)$
(a) PUN (PMOS)	$(A\text{ series }B)\parallel\bigl(C\text{ series }(D\parallel E)\bigr)$
(b) $Y$	$\overline{A}\,\overline{B}+\overline{C}\left(\overline{D}+\overline{E}\right)$

Concept & Theory

Topic: Complementary static CMOS gate synthesis (PUN/PDN duality).

Key relations: $Y=\overline{\text{PDN}_{on}}$; the PUN is the series–parallel dual of the PDN — same gate signals, opposite device type, series↔parallel swapped at every nesting level.

Why this works: the dual construction guarantees that for every input combination exactly one of PUN/PDN conducts, so the output is always driven (never floating) and never shorted between $V_{DD}$ and $V_{SS}$ — the defining property of a valid static CMOS gate.

Common pitfall: flattening a nested network before dualizing (e.g. treating $C\parallel(D\cdot E)$ as if it were a simple series or parallel group) instead of swapping series↔parallel one nesting level at a time, from the innermost group outward.

Source: Mano & Ciletti, Digital Design, Ch. 10 (CMOS logic gates); Sedra & Smith, Microelectronic Circuits, Ch. 16 (static CMOS logic).

Question 6 of 6

Question 6 (15 marks)