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04-BS-8: December 2016

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

  1. Question 1 Serial-Delay Circuit Design — Shift Register Implementation
  2. Question 2 Adders, BCD, and NAND-Gate Minimization
  3. Question 3 Memory Control Logic — Decoder and PAL Realizations
  4. Question 4 Finite State Machine Design with D Flip-Flops
  5. Question 5 Flip-Flop Conversion, Frequency Division, and Shift-Register Analysis

Start with Question 1 →

National Exams — December 2016 — 04-BS-8 Digital Logic Circuits. Three-hour, closed-book exam (Casio or Sharp approved calculator only; one hand-written 8.5"×11" aid sheet permitted). Format: five questions offered, each worth 25 marks (100 total); any four constitute a complete paper and only the first four appearing in the answer book are marked. All five are solved below for completeness.

Reference texts: Mano & Ciletti, Digital Design (6th ed., Pearson) — Boolean minimization, PAL/PLA architectures, flip-flop conversion, sequential design, arithmetic circuits, serial 2's-complement conversion; Floyd, Digital Fundamentals (11th ed., Pearson) — decoders, number systems, flip-flop characteristic tables, counters and shift registers.