Serial-Delay Circuit Design — Shift Register Implementation: 04-BS-8, December 2016, Q1

Question 1: Serial-Delay Circuit Design — Shift Register Implementation (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Required delay = 12µs; available clock = 1MHz TTL (period = 1µs); the block diagram (Figure 1) shows a single serial-in/serial-out path with no parallel load or read-out requirement — only a fixed, constant delay between Data-in and Data-out.

Find. A minimum-hardware digital circuit that delays a serial bit-stream by exactly 12µs, using the 1MHz clock.

Fig. 1 — 12-stage SISO shift register realized with a 74LS164 8-bit IC cascaded into 4 stages of a second 74LS164 (only Q0–Q3 of IC #2 are used; Q4–Q7 are left unconnected).

Approach. Since the clock period (1µs) exactly matches the delay-per-stage of a single serial-in/serial-out (SISO) D-flip-flop shift register, convert the required time delay into a required stage count and realize that stage count with the fewest standard ICs.

Part (a) — convert the time delay into clock periods. Clock period $T = 1/f = 1/1\text{MHz} = 1\,\mu\text{s}$. Each stage of a SISO shift register holds its bit for exactly one clock period before passing it to the next stage, so the number of stages needed is $$\boxed{N = \dfrac{12\,\mu\text{s}}{1\,\mu\text{s}} = 12 \text{ stages}}$$
Choose the hardware realizing 12 D-flip-flop stages with the fewest ICs. A discrete build needs 12 separate D flip-flops (12 packages, or 3 quad-D-FF ICs, plus manual interconnect). A far more economical route is to use ready-made 8-bit SISO shift-register ICs (74LS164): one 74LS164 supplies 8 of the 12 stages; a second 74LS164 supplies the remaining 4, tapping its output at internal stage Q3 (the 4th flip-flop) rather than at Q7 — the unused Q4–Q7 outputs of IC #2 are simply left open. This uses 2 ICs (16 flip-flops physically present, 12 actually used in the signal path) instead of 12 discrete flip-flop packages plus their interconnecting wiring.
Wire the clock and serial path. Serial Data-in → Serial-In of IC #1; Q7 of IC #1 → Serial-In of IC #2; Q3 of IC #2 → Serial Data-out. The 1MHz clock is bussed in parallel to the CP (clock) input of both ICs so every stage shifts on the same edge, and both MR (master reset) pins are tied to a power-on-reset line so the register starts in a known (cleared) state.

Quantity	Result
Required stage count	$N = 12\,\mu\text{s}/1\,\mu\text{s} = 12$ D flip-flop stages
Hardware	2× 74LS164 8-bit SISO shift register (12 of 16 stages used)
Wiring	Data-in→IC1 SI; IC1 Q7→IC2 SI; IC2 Q3→Data-out; common 1MHz clock and reset

Part (b) — minimum hardware & applications. The 12-stage SISO shift register is the minimum possible hardware for this specification for two reasons: (1) a fixed serial delay of exactly $N$ clock periods is, by definition, the function a shift register performs natively — no address decoding, counters, or read/write control logic (as a RAM-based delay line would require) are needed, so every flip-flop in the path is doing useful work and none can be removed without shortening the delay; (2) realizing the 12 stages from two standard 8-bit SISO ICs (rather than 12 discrete flip-flops) minimizes package count, board area, and interconnect — the theoretical minimum of exactly 12 flip-flop stages is achieved with the fewest possible IC insertions for that stage count. No gates are needed at all in the signal path (only the clock and reset busses), so gate count is also already at its practical minimum.

Two useful applications of a fixed serial delay line: (1) bit-timing alignment (deskewing) in serial communication links — compensating for a known propagation-time offset between two data channels (e.g., aligning a recovered clock or a parallel reference signal with a serial data stream arriving after cable/PCB trace delay) so that downstream logic samples the correct bit; (2) a tapped delay line for digital signal processing — e.g., generating a delayed copy of a signal for FIR filtering, correlation, or a simple digital echo/reverberation effect, where the shift register's stage-by-stage progression provides exactly-spaced delayed samples of the input.

Concept & Theory

Topic: Serial-in/serial-out (SISO) shift registers as fixed digital delay lines.

Key relations: Stage count $N = \Delta t / T_{clk}$; SISO shift-register operation $Q_i(n{+}1) = Q_{i-1}(n)$ on each active clock edge.

Why this works: A SISO register is a chain of D flip-flops where each stage's output feeds the next stage's input; on every active clock edge the entire chain shifts one position, so a bit entering at time $t_0$ appears at the $N$th output at time $t_0 + N\cdot T_{clk}$ — an exact, jitter-free digital delay with no analog drift, unlike an RC or transmission-line delay.

Common pitfall: Forgetting that the clock period must be an exact submultiple of the target delay (here $12\,\mu\text{s}/1\,\mu\text{s}=12$, an integer) — a non-integer ratio cannot be realized by a plain shift register and would require either a different clock or an edge-detection/counter scheme. Also, over-building with more stages than needed (e.g., using two full 8-stage ICs and tapping Q7 of the second, wasting 4 stages) is not "economical" even though it still produces some delay.

Source: Mano & Ciletti, Digital Design, Ch. 6 (Registers and Counters); Floyd, Digital Fundamentals, Ch. 8 (Shift Registers).

Question 1 of 5: Serial-Delay Circuit Design — Shift Register Implementation

Question 1: Serial-Delay Circuit Design — Shift Register Implementation (25 marks)