Question 5 of 5: Flip-Flop Conversion, Frequency Division, and Shift-Register Analysis

Question 5: Flip-Flop Conversion, Frequency Division, and Shift-Register Analysis (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Part (a) — Toggle FF from a D-type FF. A D flip-flop becomes a Toggle (with enable) flip-flop by feeding its D input from the XOR of its own output Q and a toggle-enable line T: $D = T \oplus Q$. When $T=1$, $D=Q'$, so on the next clock edge the flip-flop takes on the complement of its present state — it toggles. When $T=0$, $D=Q$, so the next state equals the present state — it holds. (Tying $T$ permanently to logic 1 gives an unconditional toggle-every-clock T flip-flop.)

Part (b) — Given. Input clock: 80MHz, 30% duty cycle. Required output: 20MHz, 50% duty cycle, using edge-triggered S-R flip-flops.

Find. A sequential divider circuit.

2. Determine the division ratio. $$\dfrac{80\text{MHz}}{20\text{MHz}} = 4 \implies \boxed{\text{divide-by-4}}$$
3. Realize divide-by-4 with toggling S-R flip-flops. Wire each S-R flip-flop as a toggle stage: $S=\overline{Q}$, $R=Q$ (edge-triggered), so each stage complements on every active clock edge it receives — exactly a T flip-flop built from an S-R. Cascade two such stages (FF1's output clocks FF2): FF1 divides 80MHz→40MHz, FF2 divides 40MHz→20MHz.
4. Why the output duty cycle is 50% regardless of the input's 30%. A toggle stage's output changes state exactly once per active (e.g. rising) edge of its clock input — it counts EDGES, not high/low time. Since the 80MHz source clock's edges are evenly spaced in time (period $T=12.5\text{ns}$) regardless of what fraction of each period is spent high vs. low, the time between successive toggles of FF2's output is always exactly $4T$, split into two equal $2T$ halves (high, then low) — giving an exact 50% duty cycle at 20MHz, independent of the 30% duty cycle of the source.

Part (c)(i) — Given. Figure 5: an 8-bit shift register whose serial output feeds (1) one input of an XOR gate whose OTHER input is the Q output of a JK flip-flop, and whose output recirculates back into the register's own serial input; and (2) one input of an OR gate (the JK's Q is the other input) whose output drives the JK's J input, with K permanently tied to logic 0 (so the flip-flop, cleared to 0 initially via Clr, can only be SET by J and can never be reset again except by the external clear).

Find. The circuit's main function.

6. Recognize the "sticky flag" behaviour of the JK flip-flop. With $K=0$ always, the flip-flop's next state is $Q^+ = J = (\text{bit shifting out}) + Q$ (an OR): once the shifted-out bit is a 1, $Q$ becomes 1 and then STAYS 1 for the rest of the 8-clock sequence (K=0 prevents it ever clearing again). So $Q$ acts as a one-way "have I seen a 1 yet, scanning from the LSB" flag.
7. Recognize the XOR's role. The recirculated bit is $Y = (\text{bit shifting out}) \oplus Q_{\text{flag}}$ (flag value BEFORE this clock's update): while the flag is still 0 (no 1 seen yet), $Y$ equals the bit unchanged; once the flag is 1, $Y$ is the COMPLEMENT of the bit.
8. Identify the algorithm. "Copy every bit unchanged from the LSB up to and including the first 1 encountered, then complement every bit after that" is precisely the standard bit-serial algorithm for forming the 2's complement of a binary number. $$\boxed{\text{Figure 5 is a serial (bit-serial) 2's complementer.}}$$ After exactly 8 clock cycles, every one of the 8 loaded bits has been shifted out, conditionally complemented, and recirculated back in, so the register now holds the 2's complement of the number it was loaded with.

Part (c)(ii) — worked example. Load the register with $(00101100)_2 = 44_{10}$ (LSB at the shift-out end). Simulating the circuit bit-by-bit for 8 clocks (flag starts at 0):

The recirculated bits, in the order produced, resettle into the register as $(11010100)_2$. $$\boxed{-44_{10} \to \text{2's complement } (11010100)_2}$$ matching $2^8 - 44 = 212 = (11010100)_2$ exactly.