Question 3 of 5: Memory Control Logic — Decoder and PAL Realizations

Question 3: Memory Control Logic — Decoder and PAL Realizations (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Five inputs (Select, Read-Mem, I2, I1, I0); ten active-low outputs Q0–Q9 whose activation pattern is fixed by Table 3.

Find. A minimum decoder+gate circuit realizing Table 3 exactly.

Approach. Recognize that Select=0 AND Read-Mem=0 is the ONLY condition under which any output is active, and that within that condition the remaining 3 inputs (I2,I1,I0) select exactly one of 8 codes — a textbook 3-to-8 decoder enable/select pattern. Check whether the 8 codes can be routed to the 10 outputs with no extra gates.

1. Assign the decoder's enables and select lines. Tie Select→E1 and Read-Mem→E2 (both active-low enables on a 74LS138), and E3 (active-high enable) to Vcc (logic 1). The decoder is therefore enabled ONLY when Select=0 AND Read-Mem=0 — exactly reproducing the "none" rows (Select=1 or Read-Mem=1 disables the decoder, driving all $\overline{Y_i}$ high, so every Q is inactive). Tie I2,I1,I0 → A2,A1,A0.
2. Check whether the 8 decoder codes map directly onto the 10 outputs. Tabulating Table 3 by I2I1I0 code: 000→{Q0,Q8}, 001→{Q3,Q5}, 010→{Q4}, 011→{Q6}, 100→{Q7}, 101→{Q2}, 110→{Q9}, 111→{Q1}. Exactly two codes (000 and 001) drive TWO outputs simultaneously, and the other six drive exactly one each — $2\times2 + 6\times1 = 10$ outputs from 8 codes, with no code driving zero and no output driven by more than one code. Since each output only ever needs to equal ONE decoder line (never a combination of several), no combining gates are required at all —
3. Wire outputs directly to decoder lines (fan-out, not logic). $$\boxed{Q_0=Q_8=\overline{Y_0},\ \ Q_3=Q_5=\overline{Y_1},\ \ Q_4=\overline{Y_2},\ \ Q_6=\overline{Y_3},\ \ Q_7=\overline{Y_4},\ \ Q_2=\overline{Y_5},\ \ Q_9=\overline{Y_6},\ \ Q_1=\overline{Y_7}}$$.

Part (b) — PAL16L8 implementation. A PAL16L8 provides 10 dedicated inputs and 8 dedicated active-low combinational outputs, each output being a programmable sum (OR) of up to 7 AND product terms. Because Q0 always equals Q8 and Q3 always equals Q5 (every row of Table 3 sets each pair identically), only 8 independent logic values are actually needed — {Q0(=Q8), Q3(=Q5), Q4, Q6, Q7, Q2, Q9, Q1} — which fits the PAL16L8's 8 output pins exactly, with the duplicate destinations (Q8, Q5) simply wired externally to the same pin as Q0 and Q3 respectively. The five inputs (Select, Read-Mem, I2, I1, I0) use only 5 of the 10 available dedicated input pins.

Each output needs only ONE product term (since each of the 8 signals is active for exactly one input combination, identical to the decoder-line logic above), e.g. the Q0/Q8 output's single live AND row is $\overline{\text{Select}}\cdot\overline{\text{Read-Mem}}\cdot\overline{I2}\cdot\overline{I1}\cdot\overline{I0}$ (fed by the true or complement fuse of each of the 5 relevant input lines, as required), and the PAL's active-low output buffer inverts the OR of that single term to produce the correct active-low signal directly — matching the same Boolean condition as decoder line Y0 above. On the fuse map, this means: for each of the 8 outputs, leave INTACT (do not blow) exactly the 5 input-fuses forming that output's required product term in ONE of its (up to 7) available AND rows, and blow every other fuse in that row and every fuse in all other unused rows for that output (an all-fuses-blown row contributes no term, i.e. is simply absent from the OR).

Part (c) — comparison. Both implementations realize the identical Boolean function with the identical minimum external-gate count (zero), so functionally and in raw gate economy they are equivalent for THIS problem. The decoder solution (part a) uses a single fixed-function MSI part whose internal structure cannot be altered; the PAL solution (part b) uses a single field-programmable part whose AND array can be reprogrammed to realize a completely different input/output mapping without changing the board at all. Advantages of the PAL family: (1) field reconfigurability — if the memory map or enable-output assignment changes later, only the fuse pattern is reprogrammed, not the hardware; (2) design consolidation — a PAL can absorb both the "decode" function AND any extra combinational logic (had the mapping been irregular enough to need gates beyond a plain decoder) into ONE package, whereas a fixed decoder would need separate discrete gates bolted on for any non-decoder-shaped output pattern; (3) fewer distinct part numbers to stock, since one programmable device type covers many different custom logic functions.