Short-Answer Set — Flip-Flop Conversion, Boolean Evaluation, Characteristic Tables, Memory Sizing, Gate Network: 04-BS-8, May 2016, Q3

Question 3: Short-Answer Set — Flip-Flop Conversion, Boolean Evaluation, Characteristic Tables, Memory Sizing, Gate Network (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Part (a) — Given/Find. A single-input D latch/flip-flop must be built from one SR flip-flop plus ordinary gates. Approach. Tie $S=D$ directly and drive $R=\overline{D}$ through one inverter, which guarantees $S$ and $R$ are always complementary — the SR flip-flop’s forbidden $S{=}R{=}1$ state can never occur, so its behaviour collapses exactly to $Q^{+}=D$.

D flip-flop built from one SR flip-flop: S=D, R=D′ via a single inverter.

With $S=D,\ R=\overline{D}$: on $D=1$, $(S,R)=(1,0)$ → SET, $Q^{+}=1$; on $D=0$, $(S,R)=(0,1)$ → RESET, $Q^{+}=0$. In both cases $Q^{+}=D$, confirming the conversion — only ONE inverter and the SR flip-flop itself are needed.

Part (b) — Given. $A=1,\ B=0,\ C=1$; $X = \overline{A\oplus B}\cdot C$ (the bar covers the XOR, i.e. $A$ XNOR $B$, ANDed with $C$). Find. $X$.

Evaluate the XNOR. $A\oplus B = 1\oplus 0 = 1$, so $\overline{A\oplus B}=\overline{1}=0$.
AND with C. $X = 0\cdot C = 0\cdot 1 = 0$.

Quantity	Result
$X$	$\boxed{X=0}$

Part (c) — Given. The characterization table: $(A,B)=(0,0)\to Q_n$; $(1,0)\to 0$; $(0,1)\to 1$; $(1,1)\to Q_n$. Find. Which clocked flip-flop this describes, with justification.

Derive the characteristic equation. Reading the four rows as minterms of $(A,B,Q_n)$ gives $$Q^{+} = A'B + Q_n\cdot(A \odot B)$$ (hold when $A=B$; force to $B$’s value when $A\ne B$) — verified against all 8 $(A,B,Q_n)$ combinations by brute force.
Rule out JK and D, confirm SR-type. A JK flip-flop TOGGLES at $(J,K)=(1,1)$; here $(A,B)=(1,1)$ instead HOLDS $Q_n$ — so it is not JK. A D flip-flop’s next state depends on only one input, not two independent ones — not D either. The table matches the classic SR flip-flop shape with $A=R$ (reset dominant on row 2) and $B=S$ (set on row 3), except that the normally-forbidden $S{=}R{=}1$ case is explicitly DEFINED here to hold $Q_n$ rather than left indeterminate — a common, race-free way an SR flip-flop is specified in practice (e.g. a gated/clocked SR built so simultaneous S,R cannot glitch the cross-coupled pair).

Quantity	Result
Identification	$\boxed{\text{SR flip-flop}}$ (A = Reset, B = Set; S=R=1 defined to hold)

Part (d) — Given. Memory size = 4 Kbyte, byte-wide (8-bit) read. Find. The correct (address lines, data lines) pairing among the four options.

Data lines. "Byte-wide read" means each addressed location returns one byte $\Rightarrow$ 8 data lines — this eliminates option (i)’s 32.
Address lines. 4 Kbyte $=4\times 1024=4096=2^{12}$ addressable byte locations, so exactly $\log_2 4096=12$ address lines are needed to uniquely select every byte — not 4000 (not a power of two, and conflates capacity with line count), not 14 ($2^{14}=16384$, a 16 Kbyte space), not 10 ($2^{10}=1024$, only 1 Kbyte).

Quantity	Result
Correct option	$\boxed{\text{(iii) 12 address lines and 8 data lines}}$

Part (e) — Given. The gate network below: a top gate with inputs A and (bubble-inverted) B feeding a NAND; a lower path where A is inverted then ORed with C, that result then ORed with B, and both stage outputs feeding a final NAND to produce Z. Find. The simplified Boolean expression for Z.

[Figure not reproduced: The given gate network for Q3(e), redrawn: two OR stages feed a final NAND with the top NAND(A,B′) branch. See the official exam paper.]

Trace each gate. Top gate: NAND with an inverted-B input $\Rightarrow G_1=\overline{A\cdot\overline{B}}=A'+B$. Lower path: $G_2=\overline{A}+C$ (first OR), then $G_3=B+G_2=B+A'+C$ (second OR).
Combine at the final NAND. $Z=\overline{G_1\cdot G_3}$. Since $G_1=A'+B$ and $G_3=A'+B+C=G_1+C$, the absorption law gives $G_1\cdot G_3=G_1\cdot(G_1+C)=G_1$. So $$Z=\overline{G_1}=\overline{A'+B}=A\cdot B'$$

Quantity	Result
Simplified $Z$	$\boxed{Z = A\cdot B'}$ (independent of C)

Concept & Theory

Topic: Flip-flop cross-conversion; XNOR evaluation; characteristic-equation identification; memory addressing arithmetic; Boolean network reduction via absorption.

Key relations: $D$-from-$SR$: tie $S=D,R=\overline{D}$; memory addressing: $2^{\text{address lines}}=\text{number of addressable locations}$; absorption law $X(X+Y)=X$.

Why this works: Forcing complementary S/R inputs is the standard technique for building any "narrower" flip-flop type (D, T) out of a "wider" one (SR, JK) — it removes exactly the input combination the wider device leaves ambiguous. Address-line counting is pure information theory: $n$ lines address $2^n$ distinct locations, so byte capacity and line count are related by a logarithm, not a linear scale, which is the trap in option (i).

Common pitfall: Confusing "4 Kbyte" (a byte COUNT, $4\times1024$) with "4000" as if it were the line count itself; and, for part (e), expanding the whole network into a full truth table or a bloated SOP instead of noticing the $G_3=G_1+C$ absorption shortcut that collapses two OR-fed NAND stages into a single literal-level identity.

Source: Mano & Ciletti, Digital Design, Ch. 5 (flip-flop conversion, characteristic equations) & Ch. 8 (memory addressing); Floyd, Digital Fundamentals, Ch. 7 (latches/flip-flops) & Ch. 10 (memory).

Question 3 of 5: Short-Answer Set — Flip-Flop Conversion, Boolean Evaluation, Characteristic Tables, Memory Sizing, Gate Network

Question 3: Short-Answer Set — Flip-Flop Conversion, Boolean Evaluation, Characteristic Tables, Memory Sizing, Gate Network (25 marks)