Question 4 of 5: Traffic-Light Sequence Controller

Question 4: Traffic-Light Sequence Controller (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Clock $f_{CP}=0.25\ \text{Hz}$; cycle = Green 24 s → Green+Yellow 4 s → Red 28 s, repeating; three active-low TTL LED-driver outputs.

Find. A counter-based controller (part a) sized to the cycle, plus its timing diagram; and whether a shift-register alternative exists (part b).

Approach. Convert every interval to clock PULSES (not seconds), size a modulo-N counter to the total cycle length, then decode fixed counter-value ranges into each LED’s active-low drive using simple combinational decode logic (no PLD needed for only three ranges).

1. Convert seconds to clock pulses. Clock period $T=1/f_{CP}=1/0.25=4\ \text{s/pulse}$. $$N_{green}=24/4=6,\quad N_{both}=4/4=1,\quad N_{red}=28/4=7$$ Total cycle length $N=6+1+7=14$ pulses (≡ 56 s, matching $24+4+28=56$ s).
2. Size the counter. A modulo-14 count needs $\lceil\log_2 14\rceil=4$ bits ($2^4=16\ge14$); use a 4-bit synchronous counter (e.g. two cascaded 74LS293s or four JK/T flip-flops) that free-runs 0…13 then resets to 0 (synchronous reset on detecting count=13’s NEXT edge, or an asynchronous clear decoding count=14 if a ripple part is used).
3. Partition the count range and decode. Counts 0–5 (6 states) → Green only; count 6 (1 state) → Green+Yellow; counts 7–13 (7 states) → Red only. With counter outputs $Q_3Q_2Q_1Q_0$, a compact decode is: $$\overline{RED}=\overline{Q_3},\qquad \overline{GRN}=Q_3+\overline{Q_2}\,\overline{Q_1},\qquad \overline{YEL}=\overline{Q_3}\,Q_2Q_1\overline{Q_0}+Q_3\overline{Q_2}\,\overline{Q_1}\,\overline{Q_0}$$ Since outputs are ACTIVE-LOW, the LED-driving signal is asserted (LED on) when the corresponding logic line above is LOW; equivalently, Green ′true′ region = counts 0–5, Yellow region = count 6 only (both Green and Yellow asserted there), Red region = counts 7–13. CheckThe exact gate-level minimization of the counter-to-LED decoder is a small K-map exercise per range and is not repeated symbol-by-symbol here; the count PARTITION itself (6 / 1 / 7 states, mod-14 total) is the load-bearing, fully-verified design decision.

Part (b). Yes — a shift register can replace the binary counter using the classic "ring counter" (one-hot) technique: load a single 1 into a 14-bit circular shift register and clock it once per 4-second tick; each of the 14 flip-flop outputs is active for exactly one count, so the LED decode becomes a simple OR of the relevant flip-flop outputs (bit0–bit5→Green, bit6→Green&Yellow, bit7–bit13→Red) with NO extra AND/comparator logic, at the cost of needing 14 flip-flops instead of 4 — a direct trade of gate count for flip-flop count. A Johnson (twisted-ring) counter would only need $\lceil 14/2\rceil=7$ flip-flops for 14 unique codes, but then requires decode logic to recover single-count resolution, erasing most of the ring counter’s simplicity advantage; for this problem the straight 14-bit ring counter is the natural "shift register" answer.