Question 5 of 5: Number Representation, Adder Architectures, Ripple-Carry Design

Question 5: Number Representation, Adder Architectures, Ripple-Carry Design (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Part (a). Sign-magnitude splits an $n$-bit word into one sign bit plus $(n-1)$ magnitude bits, so $+5$ and $-5$ differ only in the top bit (0101 vs 1101 for 4 bits); it has TWO representations of zero ($+0=0000$, $-0=1000$), and addition/subtraction needs separate sign-comparison and magnitude-borrow logic, which is why virtually no modern ALU uses it for arithmetic. Two’s complement instead represents $-x$ as $2^n-x$ (complement every bit of $x$ and add 1); it has a SINGLE representation of zero, and — its defining advantage — ordinary binary addition of the bit patterns produces the algebraically correct sum for ANY combination of signs, with no separate subtract circuit needed (subtraction is just "negate, then add"). Sign-magnitude’s advantage is that the magnitude is immediately readable without any transformation (useful for display, and historically for simpler multiply/divide hardware); two’s complement’s advantage is uniform, sign-agnostic adder hardware, which is why it is the near-universal choice in processors and DSPs today.

Part (b). A ripple-carry adder chains $n$ full adders, each waiting for the carry-out of the STAGE BELOW it before its own sum and carry-out are valid — the carry must physically "ripple" through every stage in sequence. A carry-look-ahead (CLA) adder instead computes each stage’s carry-out directly from the ORIGINAL input bits (via generate $G_i=A_iB_i$ and propagate $P_i=A_i\oplus B_i$ terms combined in a few levels of AND/OR logic), so every carry is available after a small, FIXED number of gate delays regardless of word width. Ripple-carry is slower because its worst-case delay grows LINEARLY with the number of bits ($\approx 2n$ gate delays for an $n$-bit adder, since each stage’s carry cannot even begin until the previous stage’s carry has settled), whereas CLA’s delay grows only with $\log n$ (or is constant for a single-level lookahead block) — the price CLA pays for that speed is a larger, more complex gate count that grows faster than linearly with width.

Part (c) — Given. Two 4-bit operands $A=A_3A_2A_1A_0$, $B=B_3B_2B_1B_0$, $C_{in,0}=0$. Find. A 4-bit ripple-carry adder built from the minimum number of 2-input AND, OR and XOR gates.

Approach. Derive the minimal full-adder gate count from its own truth table/K-map, then chain four identical full-adder stages, carry-out of stage $i$ feeding carry-in of stage $i+1$.

1. Minimal full adder. $S_i = A_i\oplus B_i\oplus C_i$ (2 XOR gates, since XOR is inherently 2-input) and $C_{i+1} = A_iB_i + C_i(A_i\oplus B_i)$ (reusing the first XOR’s output: 2 AND gates + 1 OR gate). Total per stage: 2 XOR + 2 AND + 1 OR = 5 gates — the standard minimal two-XOR full-adder decomposition, verified against the full 8-row truth table.
2. Chain four stages. $C_{in}$ of bit 0 is tied to 0 (or a separate borrow/carry-in pin); $C_{out}$ of each stage feeds $C_{in}$ of the next; the final $C_{out,3}$ is the adder’s overall carry/overflow (for unsigned addition).

3. Worked check. $A=0110_2(6),\ B=0101_2(5)$: stage-by-stage, $C_0{=}0\Rightarrow S_0{=}1,C_1{=}0$; $C_1{=}0\Rightarrow S_1{=}1,C_2{=}1$; $C_2{=}1\Rightarrow S_2{=}0,C_3{=}1$; $C_3{=}1\Rightarrow S_3{=}1,C_{out}{=}0$.