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04-BS-8 · December 2017

Question 2 of 5: Combinational Divide-by-4 Circuit

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

National Exams — December 2017 — 04-BS-8 Digital Logic Circuits. Three-hour, closed-book exam (Casio or Sharp approved calculator only; one hand-written 8.5"×11" aid sheet permitted). Format: five questions offered, each worth 25 marks (100 total); any four constitute a complete paper and only the first four appearing in the answer book are marked. All five are solved below for completeness.

Reference texts: Mano & Ciletti, Digital Design (6th ed., Pearson) — Boolean minimization, PAL/PLA/FPGA architectures, flip-flop conversion, sequential design, arithmetic circuits; Floyd, Digital Fundamentals (11th ed., Pearson) — decoders, number systems, flip-flop characteristic tables, counters.

Question 2: Combinational Divide-by-4 Circuit (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A 4-bit unsigned input A3A2A1A0 (value 0–15) is divided by the fixed constant 4, producing a Quotient and a Remainder such that N = 4·Q + R.

Find. (a) the bit-width of Q and R; (b) the truth table; (c) minimized Boolean equations for every output bit; (d) a minimum-gate implementation.

Approach. Since 4 = 22, dividing by 4 is exactly a 2-bit right shift: the top 2 bits of N form the quotient and the bottom 2 bits form the remainder, with no arithmetic at all. Build the full truth table to confirm this, then K-map each output bit against all four inputs to show each one collapses to a single literal.

  1. Part (a) — sizes. N ranges 0–15 (4 bits). Q = ⌊N/4⌋ ranges 0–3, so Quotient needs 2 bits (Qx1 Qx0). R = N mod 4 ranges 0–3, so Remainder needs 2 bits (Ry1 Ry0). $$\boxed{\text{Input: 4 bits; Quotient: 2 bits; Remainder: 2 bits}}$$
  2. Part (b) — truth table. Tabulating N = 0…15 against Q = ⌊N/4⌋ and R = N mod 4 (full table below) shows every row satisfies Qx1=A3, Qx0=A2, Ry1=A1, Ry0=A0.
  3. Part (c) — K-map per output. Plotting Qx1 on a 4-variable K-map fills exactly the 8 cells where A3=1 (a straight half-map split, no other variable matters) — the largest possible group, reducing to the single literal A3. The same half-map pattern recurs for each of the other three outputs against its own source bit: $$\boxed{Q_{x1}=A_3,\ \ Q_{x0}=A_2,\ \ R_{y1}=A_1,\ \ R_{y0}=A_0}$$ Each output depends on exactly one input bit and is already in its simplest possible form (a single literal cannot be reduced further).
  4. Part (d) — implement. Because every output equals a single input bit, the “circuit” is four direct wires and needs zero logic gates (Fig. Q2d) — dividing by a power of 2 is bit-repositioning, not computation.
Divide by 4 = 2-bit right shift (0 gates)A3A2A1A0Qx1 (MSB Q)Qx0 (LSB Q)Ry1 (MSB R)Ry0 (LSB R)
Fig. Q2(d) — dividing by 4 wires the top 2 input bits straight to the Quotient and the bottom 2 straight to the Remainder; no gates are needed.
Part (b) — full truth table
A3 A2 A1 A0NQx1 Qx0Ry1 Ry0
000000000
000110001
001020010
001130011
010040100
010150101
011060110
011170111
100081000
100191001
1010101010
1011111011
1100121100
1101131101
1110141110
1111151111
Final results — Question 2
ItemResult
Input width4 bits
Quotient width2 bits
Remainder width2 bits
Qx1, Qx0A3, A2
Ry1, Ry0A1, A0
Gate count0 (direct wiring)