Flip-Flop Conversion, Frequency Division and Serial 2’s-Complement: 04-BS-8, December 2017, Q5

Question 5: Flip-Flop Conversion, Frequency Division and Serial 2’s-Complement (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. (a) a JK flip-flop and unlimited logic gates. (b) a 60MHz, 25%-duty clock. (c) an 8-bit number pre-loaded into an 8-bit shift register.

Find. (a) a Toggle-flip-flop circuit; (b) a 15MHz, 50%-duty generator plus its timing diagram; (c) a shift-register-based 2’s-complement converter.

Approach. (a) Use the JK characteristic table directly — J=K=1 always toggles. (b) An edge-triggered toggle flip-flop halves frequency AND always outputs exactly 50% duty regardless of its input’s duty cycle, because only the edge spacing (not the pulse width) of the driving clock matters; cascade two such stages for a divide-by-4. (c) Realize the standard “copy bits up to and including the first 1, then complement every bit after it” 2’s-complement algorithm as a rotate-through-XOR shift register gated by a one-shot “seen a 1 yet” flag.

Part (a) — Toggle from JK. The JK characteristic table gives Q⁺=Q_n when J=K=0 (hold) and Q⁺=Q_n′ when J=K=1 (toggle). Tying the J and K inputs together to a single control line T therefore needs no additional gate at all — just a wire junction: $$\boxed{J=K=T:\ T=0\Rightarrow\text{hold},\ T=1\Rightarrow\text{toggle every clock}}$$ For an unconditional toggle flip-flop (as this part asks for), tie J=K=1 permanently (Fig. Q5a). Verified against the native JK table for all 4 (T,Q) combinations.
Part (b) — divide-by-4 chain. Configure each D flip-flop as a toggle stage (D tied to its own Q′, i.e. D-FF wired exactly like the T-FF of part a). The key fact: an edge-triggered flip-flop only cares WHEN its clock crosses the triggering edge, not how long the clock stays high — so even though the 60MHz input is high for only 25% of each 16.667 ns period, its positive edges are still exactly 16.667 ns apart. The first toggle stage (Q_a) therefore produces a perfectly even 30MHz, 50%-duty square wave; a second toggle stage clocked by Q_a halves it again to $$\boxed{60\text{MHz}/4 = 15\text{MHz, exactly 50\% duty}}$$ (edge times: 0, 16.667, 33.333, … ns, independent of the input duty cycle).
Part (c) — shift-register 2’s complement. The standard rule “scan from the LSB, copy bits unchanged up to and including the first 1, then complement every bit after it” is realized with one extra “sticky-one” flag flip-flop: each clock, let bit = the register’s current LSB (Q0); output bit = bit ⊕ flag (using flag’s value BEFORE this clock, so the first 1 itself is passed through unchanged); then update flag’s D input to flag + bit (it latches permanently high the cycle after the first 1 appears). Rotating that output bit back into the MSB end of the register while every other bit shifts one place towards the LSB means that after exactly 8 clock cycles — one full rotation — the register holds the 2’s complement of the original number, exactly as the question specifies. $$\boxed{\text{bit}_{out}=Q_0 \oplus \text{flag},\quad \text{flag}^+=\text{flag}+Q_0}$$ verified against 9 test values (including 0, 128, 255) by simulating all 8 rotations and comparing to 256−N mod 256.

Fig. Q5(a) — Toggle flip-flop: J and K tied together to T (unconditional toggle shown with T permanently high).

Fig. Q5(b) — two divide-by-2 stages turn the 60MHz/25%-duty clock into a 15MHz/50%-duty output; each stage’s edges stay evenly spaced regardless of duty cycle.

Fig. Q5(c) — 8-bit rotate-through-XOR shift register: the LSB is XORed with a sticky-one flag and rotated back into the MSB; after 8 clocks the register holds the 2’s complement.

Final results — Question 5
Item	Result
Toggle-FF condition	J = K = T (no gate needed)
Output frequency (part b)	15 MHz, exactly 50% duty
Divider structure	2 cascaded toggle (D-as-T) flip-flops
2’s-complement rule (part c)	bit_out = Q0 ⊕ flag; flag+ = flag + Q0
Cycles to complete	8 (one full register rotation)

Concept & Theory

Topic: Flip-flop conversion, edge-triggered frequency division, and serial 2’s-complement arithmetic.

Key relations: JK characteristic table (J=K=1 ⇒ toggle); an edge-triggered divide-by-2 stage always outputs 50% duty regardless of input duty cycle; 2’s complement = copy-through-first-1, then bitwise-complement the rest.

Why this works: A flip-flop samples its input only at the clock edge, so its output waveform’s duty cycle is set entirely by the SPACING between consecutive triggering edges of its own clock, never by that clock’s pulse width — which is exactly why a 25%-duty input still produces a clean 50%-duty divided output. The sticky-flag shift-register algorithm works because 2’s complement is equivalent to “invert then add 1,” and adding 1 to a binary number ripples a carry only until it hits the first 0 bit (i.e. flips every bit after the first 1 of the original number) — the flag flip-flop is exactly that ripple-carry memory, unrolled into a shift register instead of a combinational adder.

Common pitfall: Assuming the output duty cycle of a frequency divider depends on the input’s duty cycle (it does not, for an edge-triggered design); and, in the 2’s-complement shift register, complementing the first 1 bit itself instead of passing it through unchanged.

Source: Mano & Ciletti, Digital Design §5 (flip-flop conversion), §6 (shift registers, ripple counters); Floyd, Digital Fundamentals §9 (shift registers).

Question 5 of 5: Flip-Flop Conversion, Frequency Division and Serial 2’s-Complement

Question 5: Flip-Flop Conversion, Frequency Division and Serial 2’s-Complement (25 marks)