Question 4 of 5: Weighted-Share Voting Logic Circuit

Question 4: Weighted-Share Voting Logic Circuit (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Bob = 4 shares, Chris = 6 shares, Dave = 3 shares (13 total). Each switch is pulled up to +5V through 4.7 kΩ; closing it (voting yes) connects that line to ground. The circuit’s four outputs Y3 Y2 Y1 Y0 report the 4-bit binary total of shares voting yes.

Find. (a) the truth table; (b) minimized Boolean equations for Y3, Y2, Y1, Y0; (c) a PAL16L8 realization.

Approach. Define b, c, d = 1 when Bob, Chris, Dave respectively vote yes (the logic-level convention used for the truth table and equations — the switch itself pulls its line to ground when closed, so a Set/Reset-style buffer or an inverting sense line recovers this active-high “yes” convention from the raw switch input, exactly as an active-low pushbutton is debounced to an active-high logic signal in any switch-input design). Total yes-shares = 4b + 6c + 3d (0–13, fits in 4 bits); tabulate all 8 (b,c,d) combinations, then K-map each output bit.

1. Part (b) — Y0 (LSB). Every weight contributing an odd share count is Dave’s 3, so the sum’s LSB simply tracks d: $$\boxed{Y_0 = d}$$ (Bob’s 4 and Chris’s 6 are both even and never flip the LSB).
2. Y1. K-mapping bit-1 of the sum over (b,c,d) shows it is high exactly when c and d disagree: $$\boxed{Y_1 = c\,d' + c'\,d = c \oplus d}$$
3. Y2. K-mapping bit-2 gives three prime implicants (no larger group exists): $$\boxed{Y_2 = b\,c' + b\,d + b'\,c\,d'}$$ (bc′ and bd both fire whenever Bob votes yes with either Chris or Dave; b′cd′ is the lone case — only Chris voting yes — where bit 2 is set without Bob’s vote).
4. Y3 (MSB). Bit-3 is set only at sums 9, 10 and 13, which K-map to two 2-cell groups: $$\boxed{Y_3 = c\,d + b\,c}$$
5. Part (c) — PAL16L8. A PAL16L8 realizes any 2-level AND-OR function directly: each output line gets its own fixed OR gate fed by up to 7–8 programmable AND (product-term) rows, and the input buffers already provide both true and complemented forms of every input to the AND array. Mapping the equations above onto the device needs Y0 wired straight to d (bypassing the array entirely), Y1 two product terms (cd′, c′d), Y2 three product terms (bc′, bd, b′cd′), and Y3 two product terms (cd, bc) — all comfortably inside the 7-term-per-output budget. “Crossing the intact fuses” means leaving every AND-array intersection listed in the product-term table below connected (fused) and blowing every other intersection on that row open.