Question 1 of 5: Synchronous Up/Down Mod-8 Counter
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
04-BS-8 Digital Logic Circuits — December 2018
National Exams, 3 hours, closed book (Casio or Sharp approved calculator only; one hand-written 8.5"×11" self-prepared information sheet permitted). Format: five questions, each worth 25 marks (100 total); any four constitute a complete paper and only the first four appearing in the answer book are marked. All five are solved below for completeness.
Given. A 3-bit state $Q_2Q_1Q_0$ (mod-8), one control input $UD$ ($UD=0$: count up $0,1,\dots,7,0,\dots$; $UD=1$: count down $0,7,6,\dots,1,0,\dots$), negative-edge-triggered D flip-flops.
Find. (a) the state table; (b) minimized next-state (D-input) equations $D_2,D_1,D_0$; (c) the complete flip-flop + gate circuit.
Approach. Since $D_i=Q_i^+$ for a D flip-flop, tabulate the next state directly as $(n+1)\bmod 8$ when $UD=0$ and $(n-1)\bmod 8$ when $UD=1$ for all 8 present states, read $D_2,D_1,D_0$ straight off that table, recognize the XOR/carry structure common to binary up/down counters, then build the circuit from D flip-flops plus the resulting gate network.
Part (a) — state table. Present state (decimal and $Q_2Q_1Q_0$), and the two next states for $UD=0$ (count up) and $UD=1$ (count down):
State table — mod-8 up/down counter
Present state
Next state, UD=0 (up)
Next state, UD=1 (down)
0 (000)
1 (001)
7 (111)
1 (001)
2 (010)
0 (000)
2 (010)
3 (011)
1 (001)
3 (011)
4 (100)
2 (010)
4 (100)
5 (101)
3 (011)
5 (101)
6 (110)
4 (100)
6 (110)
7 (111)
5 (101)
7 (111)
0 (000)
6 (110)
Both columns independently reproduce the sequences given in the question (0…7… and 0,7,6,…,1…).
Part (b) — next-state equations. Because $D_i=Q_i^+$, the equations follow directly from the table. The LSB always toggles — a binary increment always flips bit 0, and so does a binary decrement — so $UD$ never enters $D_0$: $$D_0 = \overline{Q_0}$$ Bit 1 toggles whenever there is a carry into it going up ($Q_1Q_0=1$ i.e. $Q_1\cdot Q_0$) or a borrow into it going down ($Q_1Q_0=0$ i.e. $\overline{Q_1}\cdot\overline{Q_0}$); folding the direction select in, $$D_1 = Q_1\oplus Q_0\oplus UD$$ (this single XOR chain equals $Q_1\oplus Q_0$ when $UD=0$ and $Q_1\oplus\overline{Q_0}$ when $UD=1$, exactly the up- and down-toggle conditions). Bit 2 toggles on an up-carry only when $Q_1Q_0=11$ and we are counting up, or on a down-borrow only when $Q_1Q_0=00$ and we are counting down: $$\boxed{D_2 = Q_2\oplus\left(Q_1 Q_0\,\overline{UD} \;+\; \overline{Q_1}\,\overline{Q_0}\,UD\right)}$$
Part (c) — circuit implementation. Three negative-edge D flip-flops hold $Q_2,Q_1,Q_0$ on a common clock. $D_0$ wires directly from $Q_0'$ (no gate needed). $D_1$ needs two 2-input XOR gates in series ($Q_1\oplus Q_0$, then $\oplus\,UD$). $D_2$ needs: one AND2 ($Q_1\cdot Q_0$) whose output is ANDed with $\overline{UD}$ (via an inverter + AND2), one AND2 ($\overline{Q_1}\cdot\overline{Q_0}$, taken straight off the flip-flops’ own $Q'$ outputs) ANDed with $UD$, an OR2 combining the two products, and a final XOR2 with $Q_2$.
Fig. Q1(c) — complete up/down counter: 3 negative-edge D-FFs plus the $D_1,D_2$ next-state logic ($D_0=\overline{Q_0}$ is a direct feedback wire, not shown as a gate).
