04-BS-8 · December 2018
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
04-BS-8 Digital Logic Circuits — December 2018
National Exams, 3 hours, closed book (Casio or Sharp approved calculator only; one hand-written 8.5"×11" self-prepared information sheet permitted). Format: five questions, each worth 25 marks (100 total); any four constitute a complete paper and only the first four appearing in the answer book are marked. All five are solved below for completeness.
Reference texts: Mano & Ciletti, Digital Design (6th ed., Pearson) — Boolean minimization, K-maps, PAL/PLA/FPGA architectures, flip-flop conversion, sequential-circuit design, arithmetic circuits, 2’s-complement arithmetic; Floyd, Digital Fundamentals (11th ed., Pearson) — logic gates, multiplexers, shift registers, flip-flop characteristic tables, adders/subtractors.
Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.
Given. A 4-bit active-HIGH hex value $X_3X_2X_1X_0$ (0–F) and the fully-specified 16-pattern Braille dot table above (K,L,M,N, all active-HIGH, no don’t-cares — every one of the 16 hex digits has a defined pattern).
Find. (a) minimized SOP equations for K, L, M, N. (b) a 2-input-NAND-only realization of K and M.
Approach. Read the four output columns straight off the given dot table (one minterm list per output), K-map/Quine–McCluskey-minimize each of the four fully-specified 4-variable functions, brute-force-verify every minimized expression against all 16 rows, then convert K’s and M’s SOP into an all-NAND network by AND→double-NAND and OR→NAND-of-inverted-inputs.
[Figure not reproduced: Fig. Q5 — the 16 given Braille dot patterns (filled = raised dot), redrawn from the source legend as a verification aid. See the official exam paper.]
| Hex (X3X2X1X0) | K | L | M | N |
|---|---|---|---|---|
| 0 (0000) | 1 | 1 | 1 | 1 |
| 1 (0001) | 0 | 1 | 0 | 1 |
| 2 (0010) | 1 | 0 | 1 | 1 |
| 3 (0011) | 1 | 1 | 0 | 1 |
| 4 (0100) | 1 | 1 | 1 | 0 |
| 5 (0101) | 1 | 0 | 0 | 1 |
| 6 (0110) | 0 | 1 | 1 | 1 |
| 7 (0111) | 1 | 0 | 1 | 0 |
| 8 (1000) | 0 | 1 | 1 | 0 |
| 9 (1001) | 1 | 0 | 0 | 1 |
| A (1010) | 0 | 1 | 0 | 1 |
| B (1011) | 1 | 0 | 1 | 1 |
| C (1100) | 1 | 1 | 0 | 1 |
| D (1101) | 1 | 1 | 1 | 0 |
| E (1110) | 0 | 1 | 1 | 0 |
| F (1111) | 0 | 0 | 0 | 0 |
| Output | Minimized SOP |
|---|---|
| K | $X_2\overline{X_1}+\overline{X_3}\,\overline{X_2}\,\overline{X_0}+\overline{X_3}X_1X_0+X_3\overline{X_2}X_0$ |
| L | $\overline{X_3}\,\overline{X_2}X_0+X_2\overline{X_0}+X_3\overline{X_0}+X_3X_2\overline{X_1}+\overline{X_3}\,\overline{X_2}\,\overline{X_1}$ |
| M | $\overline{X_3}\,\overline{X_0}+\overline{X_3}X_2X_1+\overline{X_2}\,\overline{X_1}\,\overline{X_0}+X_3\overline{X_2}X_1X_0+X_3X_2\overline{X_1}X_0+X_2X_1\overline{X_0}$ |
| N | $\overline{X_2}X_0+\overline{X_2}X_1+\overline{X_3}\,\overline{X_2}+\overline{X_3}\,\overline{X_1}X_0+\overline{X_3}X_1\overline{X_0}+X_3X_2\overline{X_1}\,\overline{X_0}$ |
Part (b) — K and M with 2-input NAND gates only. K has 4 product terms (2–3 literals each) and M has 6 (3–4 literals each). Build every product term as a chain of 2-input NAND+inverter pairs (each pair is exactly a 2-input AND: $\overline{\overline{xy}}=xy$), then combine the resulting terms in a binary tree of NAND-of-inverted-inputs gates (each such gate is exactly a 2-input OR: $\overline{\bar a\bar b}=a+b$ by De Morgan). Both substitutions are exact, so the finished networks compute $K$ and $M$ using nothing but 2-input NAND gates (plus the input-side inverters, themselves NAND gates with tied inputs).
| Output | 2-input-NAND gate count |
|---|---|
| K | 10 two-input NAND gates on distinct signals (7 in the 4 product-term chains + 3 in the 3-stage OR tree) + 17 inverters (each itself a NAND with tied inputs: 13 internal + 4 shared input-complement taps) = 27 NAND packages total |
| M | 18 two-input NAND gates on distinct signals (13 in the 6 product-term chains + 5 in the 5-stage OR tree) + 27 inverters (23 internal + 4 shared input-complement taps) = 45 NAND packages total |