Question 2 of 7: MOS Amplifier with Current-Mirror Active Load
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
17-Comp-A1, Electronics — National Exams, December 2018. Open-book, 3 hours; seven 20-mark questions, five to be marked (all seven answered below as a complete study resource). All diodes $V_D=0.7\text{V}$ unless stated otherwise.
Reference texts: Sedra & Smith, Microelectronic Circuits (diode limiters, MOSFET/BJT small-signal amplifiers, active loads and current mirrors, op-amp imperfections, CMOS logic, oscillators) — the single reference text covering every question on this paper.
Question 2: MOS Amplifier with Current-Mirror Active Load (20 marks)
Given. $Q_3$ (PMOS, diode-connected, source at $+5\text{V}$) mirrors the reference current $I=500\mu A$ 1:1 into $Q_2$ (PMOS, source at $+5\text{V}$, drain at $V_o$), which acts as the active load for $Q_1$ (NMOS, source grounded, gate$=V_i$, drain$=V_o$).
Given data
Quantity
Value
$I$
$500\mu A$
$k_n'(W/L)_1$
$1\text{ mA/V}^2$
$k_p'(W/L)_{2,3}$
$1/3\text{ mA/V}^2$
$V_{tn}=|V_{tp}|$
$1.0\text{V}$
$V_A$ (all devices)
$80\text{V}$
$R_L$ (part d)
$50\Omega$
Find. Small-signal model parameters, $R_i$, $R_o$, open-circuit gain $A_{v,oc}$, loaded gain with $R_L=50\Omega$.
Fig. Q2-a — Small-signal AC equivalent. $Q_1$'s gate is an open circuit (infinite $R_i$); its drain drives $v_o$ through $g_{m1}v_{gs1}$ in parallel with $r_{o1}$. $Q_2$'s gate sits at AC ground (fed only by the diode-connected mirror off an ideal current source), so $v_{gs2}=0$ and $Q_2$ contributes only $r_{o2}$ to the output node.
Approach. Find the shared DC bias current from the 1:1 mirror, compute $g_m,r_o$ for $Q_1$ and $Q_2$, note that $Q_2$'s gate carries no AC signal (so it degenerates to $r_{o2}$ only), then read the gain and resistances directly off the single-node output circuit.
Part (a) — bias currents and model parameters. $Q_3$ is diode-connected and forced to $I_{D3}=I=500\mu A$ by the current source; the 1:1 mirror sets $I_{D2}=500\mu A$, and KCL at the $V_o$ node (no other DC path) forces $I_{D1}=I_{D2}=500\mu A$ too.
$$g_{m1}=\sqrt{2k_n'(W/L)_1 I_{D1}}=\sqrt{2(1\text{mA/V}^2)(0.5\text{mA})}=\boxed{1.00\text{ mA/V}}$$
$$g_{m2}=\sqrt{2k_p'(W/L)_2 I_{D2}}=\sqrt{2(1/3\text{mA/V}^2)(0.5\text{mA})}=0.577\text{ mA/V}$$
$$r_{o1}=r_{o2}=\frac{V_A}{I_D}=\frac{80\text{V}}{0.5\text{mA}}=\boxed{160\text{ k}\Omega\text{ (each)}}$$
Part (b) — input and output resistance. $Q_1$'s gate draws no DC or AC current, so
$$R_i=\infty\text{ (ideal MOSFET gate)}$$
Zeroing $v_i$ kills the dependent source $g_{m1}v_{gs1}$ (since $v_{gs1}=v_i=0$), leaving only the two output resistances in parallel:
$$R_o=r_{o1}\|r_{o2}=\frac{(160\text{k})(160\text{k})}{160\text{k}+160\text{k}}=\boxed{80\text{ k}\Omega}$$
Part (c) — open-circuit voltage gain. With $v_{gs1}=v_i$ (source grounded) and $Q_2$ contributing only $r_{o2}$:
$$A_{v,oc}=\frac{v_o}{v_i}=-g_{m1}(r_{o1}\|r_{o2})=-(1.00\text{mA/V})(80\text{k}\Omega)=\boxed{-80.0\text{ V/V}}$$
Part (d) — gain with $R_L=50\Omega$ load. Adding $R_L$ in parallel with $r_{o1}\|r_{o2}$ (a $50\Omega$ load is tiny next to $80\text{k}\Omega$, so it dominates):
$$R_L'=r_{o1}\|r_{o2}\|R_L=\frac{1}{\frac{1}{160\text{k}}+\frac{1}{160\text{k}}+\frac{1}{50}}=49.97\ \Omega$$
$$A_{v,L}=-g_{m1}R_L'=-(1.00\text{mA/V})(49.97\,\Omega)=\boxed{-0.0500\text{ V/V}}$$
The stage has almost no ability to drive a $50\Omega$ load — a direct consequence of its very high open-circuit output resistance.
