Question 6 of 7: CMOS Complex-Gate Transistor Sizing

Question 6: CMOS Complex-Gate Transistor Sizing (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Reference (unit) inverter: NMOS $(W/L)_n=1.5$, PMOS $(W/L)_p=6$ (a symmetric inverter, so this pair is the "one unit of drive strength" for both pull-up and pull-down networks).

Find. Transistor-level schematics and worst-case sizing for $Y=\overline{(AB+C)D}$ and for $Y=\overline{A\oplus B}$ (XNOR), plus the max/min drive-current ratio for the second gate.

Approach. Build the NMOS pull-down network (PDN) as the literal series/parallel switch realization of $F=(AB+C)D$ (PDN conducts — pulling $Y$ low — exactly when $F=1$); build the PMOS pull-up network (PUN) as its series↔parallel dual. Then size every transistor at (number of transistors in ITS OWN longest series path)$\times$(unit W/L), which is the standard worst-case rule that guarantees every single-input transition matches or beats the reference inverter's drive current.

1. Part (a) — schematic. $F=(AB+C)D=D\cdot\big[(A\cdot B)+C\big]$. PDN: $D$ in series with a parallel combination of ($A$ series $B$) and $C$ (see figure). PUN is the dual: $D$ in parallel with a series combination of $C$ and ($A$ parallel $B$).
2. Part (b) — worst-case sizing. The PDN's two root-to-ground paths are $D\text{-}C$ (2 transistors in series) and $D\text{-}A\text{-}B$ (3 in series); each transistor is sized by the LONGEST series path it belongs to: $$\big(W/L\big)_{D,n}=\big(W/L\big)_{A,n}=\big(W/L\big)_{B,n}=3\times1.5=\boxed{4.5}$$ $$\big(W/L\big)_{C,n}=2\times1.5=\boxed{3.0}$$ The PUN's two paths (VDD-to-$Y$) are $D$ alone (length 1) and $C\text{-}A$ / $C\text{-}B$ (length 2), so: $$\big(W/L\big)_{D,p}=1\times6=\boxed{6.0}$$ $$\big(W/L\big)_{C,p}=\big(W/L\big)_{A,p}=\big(W/L\big)_{B,p}=2\times6=\boxed{12.0}$$
3. Part (c) — XNOR gate schematic and sizing. $F=A\oplus B=\overline{A}B+A\overline{B}$, so $Y=\overline{F}=A\,\text{XNOR}\,B$. PDN $=$ parallel of two series branches, ($\overline{A}$ series $B$) and ($A$ series $\overline{B}$); PUN is the dual, series of two parallel groups, ($\overline{A}$ parallel $B$) then ($A$ parallel $\overline{B}$). Every discharge/charge path here is exactly 2 transistors long, so every device gets the SAME size: $$\big(W/L\big)_n=2\times1.5=\boxed{3.0}\text{ (all four NMOS)}$$ $$\big(W/L\big)_p=2\times6=\boxed{12.0}\text{ (all four PMOS)}$$ (Complements $\overline{A},\overline{B}$ are assumed available, e.g. from two extra unit inverters, giving 12 transistors total for a fully static realization.)
4. Part (d) — max/min drive-current ratio. Because BOTH possible discharge paths in part (c) are 2 equal-size series NMOS, the effective drive is identical for every input transition: $$\big(W/L\big)_{\text{eff,path}}=\left(\frac{1}{3.0}+\frac{1}{3.0}\right)^{-1}=1.5=\text{unit NMOS strength (both paths)}$$ and likewise every PUN path gives $\big(W/L\big)_{\text{eff}}=6.0$ (unit PMOS strength). Since every path — whichever input pair switches — delivers exactly the reference inverter's current, the ratio of maximum to minimum available drive current is $$\boxed{\dfrac{I_{\max}}{I_{\min}}=1:1}$$ unlike the part (a)/(b) gate, whose $D\text{-}C$ and $D\text{-}A\text{-}B$ paths are different lengths and so would NOT give a 1:1 ratio.