Find. $(W/L)_n,(W/L)_p$ for a symmetric VTC; max $C_L$ for $t_p<200\text{ps}$; the $X,Y$ truth table for Fig.8; minimum $(W/L)$ for $Q_5,Q_6$.
Approach. Symmetric switching needs matched drive strength $k_n'(W/L)_n=k_p'(W/L)_p$; delay follows from the (matched, so equal) saturation currents driving $C_L$ through half a $V_{DD}$ swing; the latch's truth table follows from tracing which pull-down wins against the cross-coupled PMOS; the Q5/Q6 sizing repeats the drive-matching idea against the already-sized PMOS pull-up.
Part (a) — symmetric sizing. A symmetric VTC (switching threshold exactly at $V_{DD}/2$, since $V_{tn}=|V_{tp}|$) requires equal drive strength: $k_n'(W/L)_n=k_p'(W/L)_p$. Choosing the NMOS at minimum size, $(W/L)_n=1$ ($W_n=L_n=1\,\mu\text{m}$):
$$(W/L)_p=\frac{k_n'}{k_p'}(W/L)_n=\frac{50}{20}=\boxed{2.5}\ \ (W_p=2.5\,\mu\text{m},\,L_p=1\,\mu\text{m})$$
Fig. Q6(a) — symmetric VTC obtained by matching kn'(W/L)n=kp'(W/L)p=50μA/V² ((W/L)n=1, (W/L)p=2.5): the switching threshold VM sits exactly at VDD/2=2.5V.
Part (b) — max $C_L$ for $t_p<200\text{ps}$. Model each transition with the switching device's saturation current at full-rail gate drive ($|V_{GS}|=V_{DD}$), delivering a $\Delta V=V_{DD}/2$ swing: $t_p=C_L(V_{DD}/2)/I_D$. Since the sizing above makes NMOS and PMOS drive strengths equal ($k_n'(W/L)_n=k_p'(W/L)_p=50\,\mu\text{A/V}^2$), both edges give the same current:
$$I_D=\tfrac12k_n'(W/L)_n(V_{DD}-V_{tn})^2=\tfrac12(50\mu\text{A/V}^2)(1)(4)^2=400\,\mu\text{A}$$
$$C_{L,\max}=\frac{t_p\cdot I_D}{V_{DD}/2}=\frac{(200\text{ps})(400\mu\text{A})}{2.5\text{V}}=\boxed{32\text{ fF}}$$
Part (c) — Fig.8 truth table. When $\phi=0$: both write ports are cut off (Q6,Q8 off), so $X,Y$ simply HOLD their previous state via the cross-coupled inverters, regardless of $A,B$. When $\phi=1$: if $A=1,B=0$, $Q_6$+$Q_5$ pull $X$ low, which (once $X$ drops) turns $Q_4$ on hard and $Q_3$ off, driving $Y$ high — and $Y=1$ then turns $Q_1$ on/$Q_2$ off, reinforcing $X=0$ regeneratively (stable SET state $X=0,Y=1$). Symmetrically $A=0,B=1$ gives stable $X=1,Y=0$. $A=0,B=0$ (with $\phi=1$) leaves both pull-downs off, so the latch again just holds its previous state. $A=1,B=1$ simultaneously drives both $X$ and $Y$ low at once — contention between the two cross-coupled halves — an invalid/forbidden input combination (exactly analogous to $S=R=1$ in a classic SR latch).
Question 6(c) — truth table for Fig.8
$\phi$
$A$
$B$
$X$
$Y$
Notes
0
×
×
hold
hold
write ports cut off
1
0
0
hold
hold
no pull-down active
1
1
0
0
1
SET: X pulled low, regenerates
1
0
1
1
0
RESET: Y pulled low, regenerates
1
1
1
invalid
invalid
forbidden (both pulled low at once)
Part (d) — sizing $Q_5,Q_6$. Worst case: $X=1,Y=0$ currently (so $Q_2$'s gate $=Y=0$, fully ON, fighting the write), and we attempt $A=1,\phi=1$ to pull $X$ down to $V_{DD}/2$. At that exact node voltage, PMOS $Q_2$ has $V_{SG}=V_{DD}-0=5\text{V}$, overdrive $V_{ov}=5-1=4\text{V}$, and $V_{SD}=V_{DD}-V_{DD}/2=2.5\text{V}\lt V_{ov}$, so $Q_2$ is in TRIODE (not saturation). The series NMOS pair $Q_6,Q_5$ (both driven full-rail, $V_{GS}=V_{DD}=5\text{V}$, same overdrive $4\text{V}$) sees the SAME $V_{ov}=4\text{V}$ and the same $2.5\text{V}$ drop across the stack — because both devices share identical overdrive and drain-source drop, the triode bracket terms cancel identically, and the sizing condition reduces to the same drive-matching rule as part (a):
$$k_n'(W/L)_{\text{eff}}=k_p'(W/L)_p\ \Rightarrow\ (W/L)_{\text{eff}}=\frac{k_p'(W/L)_p}{k_n'}=\frac{20(2.5)}{50}=1$$
Modelling the two identical series NMOS as one device with half the effective aspect ratio, $(W/L)_{\text{eff}}=(W/L)_{\text{each}}/2$:
$$(W/L)_{Q_5}=(W/L)_{Q_6}=\boxed{2}\ \ (W=2\,\mu\text{m},\,L=1\,\mu\text{m}\text{ each})$$
Final Results — Question 6
Quantity
Value
$(W/L)_n$
$1$ (minimum)
$(W/L)_p$
$2.5$
$C_{L,\max}$ for $t_p<200\text{ps}$
$32\text{ fF}$
Fig.8 valid states
hold / SET(0,1) / RESET(1,0); $A{=}B{=}1$ forbidden
