Given. Five equal $10\text{k}\Omega$ resistors from $V_{ref}=5\text{V}$ to ground (4 taps); each comparator's $+$ input tied to $V_{in}$, $-$ input tied to a ladder tap; $V_{in}=3\text{V}$ for part (b).
Given data
Quantity
Value
$V_{ref}$
$5\text{V}$
Ladder
5 × $10\text{k}\Omega$ (4 taps)
$V_{in}$ (part b)
$3\text{V}$
Find. ADC name and advantage; the four threshold voltages and resulting logic values at $V_{in}=3\text{V}$; the full $V_1$-$V_4$ → binary-output table; how $V_{ref}$ is generated on-chip.
Approach. Each comparator fires (output 1) once $V_{in}$ exceeds its own ladder-tap reference; since the taps are evenly spaced and $V_{in}$ is common to all, the outputs always form a "thermometer code" whose count of 1's directly equals the quantized level.
Part (a) — name and advantage. This is a flash (parallel) ADC. Its principal advantage is CONVERSION SPEED: all comparisons happen simultaneously in one clock edge (a single comparator delay), making it the fastest ADC architecture — unlike successive-approximation or dual-slope converters, which need multiple clock cycles per sample. The tradeoff (not asked, but the reason it's used only for low-to-moderate resolution) is that it needs $2^N-1$ comparators for $N$ bits.
Part (b) — thresholds and logic values. Each tap divides $V_{ref}$ into fifths: from top to bottom, the four comparator (−) references are
$$V_4^{ref}=4\text{V},\ \ V_3^{ref}=3\text{V},\ \ V_2^{ref}=2\text{V},\ \ V_1^{ref}=1\text{V}$$
For $V_{in}=3\text{V}$: $V_{in}>V_2^{ref},V_1^{ref}$ (comparators fire), $V_{in}=V_3^{ref}$ exactly (boundary, taken as firing by the $\ge$ convention), and $V_{in}<V_4^{ref}$ (does not fire):
$$V_4=0,\quad V_3=1,\quad V_2=1,\quad V_1=1$$
Fig. Q7 — four equal-spaced comparator thresholds from the R-ladder (Vref/5 per tap); Vin=3V sits exactly on the V3 threshold, taken as the boundary (≥) convention.
Part (c) — full combination table. Because $V_{in}$ is monotonic and common to every comparator, only the five "thermometer code" patterns below ever actually occur (all-0 up to some point, then all-1 above it); any other combination (e.g. $0101$) cannot arise from a real, single-valued $V_{in}$ and is a don't-care for the encoder logic.
Question 7(c) — valid $V_4V_3V_2V_1$ combinations and binary output
$V_{in}$ range
$V_4$
$V_3$
$V_2$
$V_1$
Binary output
$V_{in}<1\text{V}$
0
0
0
0
000 (0)
$1\le V_{in}<2\text{V}$
0
0
0
1
001 (1)
$2\le V_{in}<3\text{V}$
0
0
1
1
010 (2)
$3\le V_{in}<4\text{V}$
0
1
1
1
011 (3)
$V_{in}\ge4\text{V}$
1
1
1
1
100 (4)
Part (d) — generating $V_{ref}$ on-chip. A precision, temperature- and process-independent reference is normally generated with a bandgap reference circuit (combining a $V_{BE}$'s negative temperature coefficient with a scaled $\Delta V_{BE}$'s positive coefficient to cancel drift, per Widlar/Brokaw-style topologies), buffered through an op-amp to drive the resistor ladder at low output impedance so ladder-current loading doesn't sag the taps.
