Question 2 of 6

Question 2 (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. (a) 16-bit registers A=0xFFFE, B=0x0012 (the source shows "0x FFFE" with a stray space). (b) the paper's single-precision format: 1 sign bit S, 8-bit exponent E with bias 128 (so stored value represents $E-128$), 23-bit mantissa M, arbitrary floats A and B. (c) a 64-row × 32-column array of 16-bit (2-byte) elements, base address 0x1000.

Find. (a) A+B in decimal under both interpretations, with the overflow behaviour explained. (b) whether the product A×B is always exactly representable; if not, how many extra bits each field needs in the worst case. (c) the storage scheme and the address formula for A[R][C].

Approach. (a) add the raw 16-bit patterns exactly once, then interpret that SAME result two different ways and apply each interpretation's own overflow rule. (b) bound the significand product's bit-length and the summed exponent's range against the fields the format actually provides. (c) apply the standard row-major 2-D array address formula (stating the row-major assumption, since the source does not specify an ordering).

1. Part (a) — A+B under both interpretations. The processor adds the same 16-bit patterns regardless of interpretation: $\text{0xFFFE}+\text{0x0012}=65534+18=65552$ as a true unsigned sum — but a 16-bit register only holds values $0$–$65535$, so the stored result keeps only the low 16 bits, $65552\bmod65536=16$ (0x0010), and the discarded carry means the unsigned interpretation overflows (the true sum exceeds the largest representable unsigned value). Under 2's-complement signed interpretation, 0xFFFE reads as $-2$ and 0x0012 reads as $+18$ (its top bit is 0, so it is positive under either reading), giving a true signed sum of $-2+18=+16$, which sits comfortably inside the 16-bit signed range $[-32768,32767]$ — no signed overflow. The STORED BIT PATTERN is identical either way (0x0010, i.e. decimal 16); only the overflow-detection rule differs between the two interpretations, because they partition the same $2^{16}$ bit patterns differently. $$\boxed{\text{unsigned: true sum }65552\text{, overflows, register reads }16;\ \ \text{signed: true sum }+16\text{, no overflow}}$$
2. Part (b) — can a product always be exact? Each operand's significand is $1.M$, representable as a 24-bit fixed-point integer (1 implicit + 23 explicit fraction bits) ranging up to $2^{24}-1=16{,}777{,}215$. The EXACT product of two such 24-bit integers can need up to $\lceil\log_2\left((2^{24}-1)^2\right)\rceil=48$ bits — almost double the original 24 — so the mantissa field must grow by up to $48-24=24$ explicit bits in the worst case to hold the exact product before any rounding. The product's true exponent is the SUM of the two operands' exponents: with an 8-bit field and bias 128, each stored exponent value $E-128$ ranges over $-128$ to $127$ (256 distinct values), so the summed exponent ranges over $-256$ to $254$ (511 distinct values) — nearly double the 256 code points the current 8-bit field can distinguish, so the exponent field needs $\lceil\log_2(511)\rceil=9$ bits, i.e. 1 more bit, in the worst case. The sign of the product is simply $S_A\oplus S_B$ (XOR of the two input signs), which always fits in the SAME single bit the format already has, so 0 additional sign bits are ever needed. $$\boxed{\text{not always exact; needs up to }24\text{ more mantissa bits, up to }1\text{ more exponent bit, }0\text{ more sign bits}}$$
3. Part (c) — 2-D array storage and addressing. With no ordering stated in the question, the standard convention is assumed: the array is stored row-major — all 32 elements of row 0 occupy consecutive memory first, then all 32 elements of row 1, and so on through row 63, each element taking 2 bytes (16 bits). The address of element A[R][C] is the base plus the element size times how many elements precede it (all of rows $0..R-1$, i.e. $R\times32$ elements, plus the $C$ elements before it in row $R$): $$\text{addr}(A[R][C])=\text{0x1000}+2\times(32R+C)$$ The whole array occupies $64\times32\times2=4096$ bytes ($0\text{x}1000$ bytes), i.e. addresses 0x1000 through 0x1FFF inclusive. $$\boxed{\text{addr}(A[R][C])=\text{0x1000}+2(32R+C)}$$