25-Comp-A3 Computer Architecture, December 2018, Q5

Question 5 (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given.

Given data — Question 5
Instruction type	Frequency	Cycles (original)	Cycles (modified)
LI (load immediate)	10%	4	5
ARITHMETIC	50%	3	3
MEMORY READ	20%	5	5
MEMORY STORE	10%	4	4
BRANCH	10%	3	3

The modified implementation's clock frequency is 3% higher than the original's (so its cycle time is the original's divided by 1.03).

Find. Which implementation runs the given instruction mix faster, and by how much.

Approach. Compute each design's CPI as the frequency-weighted average cycle count, then compare TIME per instruction ($\text{CPI}\times\text{cycle time}$) rather than CPI alone, since the two designs run at different clock rates.

Step 1 — CPI of the original implementation. Weighting each instruction type's cycle count by its frequency: $$\text{CPI}_{\text{orig}}=0.10(4)+0.50(3)+0.20(5)+0.10(4)+0.10(3)=0.4+1.5+1.0+0.4+0.3$$ $$\boxed{\text{CPI}_{\text{orig}}=3.6\ \text{cycles/instruction}}$$
Step 2 — CPI of the modified implementation. Only the LI row changes, from 4 to 5 cycles: $$\text{CPI}_{\text{mod}}=0.10(5)+0.50(3)+0.20(5)+0.10(4)+0.10(3)=0.5+1.5+1.0+0.4+0.3$$ $$\boxed{\text{CPI}_{\text{mod}}=3.7\ \text{cycles/instruction}}$$ CPI alone already shows the modified design needs MORE cycles per instruction on average — but cycles are not seconds, so this cannot yet decide which is faster.
Step 3 — compare TIME per instruction, not CPI. Let $T$ be the original implementation's cycle time; the modified clock is 3% faster, so its cycle time is $T/1.03$. Time per instruction is $\text{CPI}\times\text{cycle time}$: $$\text{Time}_{\text{orig}}=3.6\times T=3.6\,T$$ $$\text{Time}_{\text{mod}}=3.7\times\frac{T}{1.03}=3.592233\,T$$ Since $3.592233\,T<3.6\,T$, the modified implementation IS faster, despite its higher CPI, because the 3% clock-speed gain outweighs the extra cycle it costs LI — an instruction type that is only 10% of the mix. The speedup factor is: $$\text{speedup}=\frac{3.6}{3.592233}=1.002162$$ $$\boxed{\text{modified implementation is faster, by about }0.22\%}$$

Final results — Question 5
Quantity	Original	Modified
CPI	3.6	3.7
Cycle time	$T$	$T/1.03$
Time/instruction	$3.6\,T$	$3.592233\,T$
Winner	$\boxed{\text{Modified, by} \approx 0.22\%}$

Topic: CPI-vs-clock-rate tradeoff when redesigning a multi-cycle datapath/control unit.

Key relations: $\text{CPI}=\sum_i \text{freq}_i\times\text{cycles}_i$; $\text{time per instruction}=\text{CPI}\times T_{\text{clock}}$; comparing two designs with DIFFERENT clock rates requires comparing this TIME, never CPI alone.

Why this works: a redesign that both worsens CPI (an extra cycle on one instruction type) and speeds the clock can win or lose purely on how the two multiplicative factors trade off; only their PRODUCT is a valid performance measure. Here the extra LI cycle is diluted by LI's modest 10% frequency, so it costs less overall CPI than the flat 3% clock gain saves.

Common pitfall: comparing $\text{CPI}_{\text{orig}}$ vs. $\text{CPI}_{\text{mod}}$ directly and declaring the original faster because it has the smaller CPI, ignoring that the modified design's clock is also faster; forgetting that an instruction-mix WEIGHT (not just a cycle-count change) determines how much a single row's penalty actually costs.

Source: Patterson & Hennessy, Computer Organization and Design, 6th ed., Ch.1 (performance equations, CPI) & Ch.4 (multicycle datapath and control).

Question 5 of 6

Question 5 (20 marks)