25-Comp-A3 Computer Architecture, December 2018, Q6

Question 6 (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Check: the paper's description of part (a)'s data pins is self-contradictory — it prints "the four D1-D3 single bit output/input pins" (naming only 3 pins, D1-D3, while saying "four") and then "When E is 0 the D1-D0 pins are in high-Z" (only 2 of those). We adopt 4 data pins (read as D3-D0), since "four" is the more specific quantity given and the design in parts (b)/(c) is clean and self-consistent under it (two 4-bit-wide chips compose exactly into the required 8-bit width with no leftover bits); the "D1-D0" phrase is treated as a misprint for the same pins rather than a second, smaller pin count.

Given. (a) a memory chip: 22 address lines A0–A21, a chip-enable E, a read/write control R/W!, and (per the check note above) 4 bidirectional data pins. (b) target: an 8-bit-wide, 8MB-total memory built from copies of this chip. (c) a processor interface with 32 address lines L0–L31, an access-enable ME, R/W!, and 8 bidirectional data lines D0–D7; the module must respond only to the 8MB range starting at 0x10000000.

Find. (a) the chip's total capacity in bytes. (b) how many chips (and what wiring/decode logic) synthesizes the target memory. (c) how to connect one such 8MB module to the processor's interface so it activates only for its assigned address range.

Approach. (a) count addressable rows from the address-line count, multiply by data-pin width, convert to bytes. (b) split the requirement into a width-expansion factor (target width / chip width) and a depth-expansion factor (target rows / chip rows), then combine, adding one address-decoded selector bit for the depth split. (c) separate the LOW address bits that index WITHIN the module (feeding the chips directly, including the depth-select bit from (b)) from the HIGH address bits that must match a fixed pattern to select the WHOLE module.

Part (a) — chip capacity. 22 address lines address $2^{22}=4{,}194{,}304$ distinct rows, each 4 bits wide: $$\text{total bits}=4{,}194{,}304\times4=16{,}777{,}216\ \text{bits}$$ $$\boxed{\text{total capacity}=16{,}777{,}216/8=2{,}097{,}152\ \text{bytes}=2\ \text{MB}}$$
Part (b) — composing an 8-bit×8MB memory. Width expansion: the target word is 8 bits wide but each chip only supplies 4, so 2 chips placed side-by-side (sharing all address lines, E, and R/W!, but each contributing a different half of the data bus — one supplies D3–D0, the other D7–D4) are needed per addressable byte: $$\text{width chips}=8/4=2$$ Depth expansion: one such width-group of 2 chips already spans the chip's own $4{,}194{,}304$ addresses at 1 byte per address, i.e. 4MB; the target is 8MB, so 2 depth groups are needed: $$\text{depth groups}=\lceil 8\,\text{MB}/4\,\text{MB}\rceil=2$$ $$\boxed{\text{total chips}=2\times2=4}$$ Because 2 divides evenly, only 1 extra address bit (call it A22, beyond the chip's own A0–A21) is needed to pick between the two depth groups — a simple 1-of-2 decoder (an inverter feeding one group's E input, the bit itself feeding the other's) drives exactly one group's chip-enables at a time, with no partial/uneven decode logic required.
Part (c) — connecting one 8MB module to the processor bus. The module needs $\log_2(8\,\text{MB})=23$ address bits (L22–L0) to index every byte inside it: L21–L0 (22 bits) feed directly into every one of the 4 chips' shared A21–A0 inputs, and L22 is exactly the depth-select bit from part (b), feeding the 1-of-2 decoder built there. The remaining 9 high-order lines, L31–L23, together with ME, must be compared against the FIXED pattern for base address 0x10000000 (a 9-input AND/comparator gate) to produce the module's overall select signal, since the module must respond only when the address falls within 0x10000000–0x107FFFFF. Because 0x10000000 is exactly 8MB-aligned (its low 23 bits are all zero), this is a clean fixed-pattern compare with no extra offset arithmetic. R/W! connects directly to every chip's own R/W! input (all 4 chips see the identical signal); D0–D3 wire to both depth groups' low-half chips (D3–D0 pins) and D4–D7 to both groups' high-half chips (D3–D0 pins on those chips), which is safe because only one depth group is ever enabled at a time. L22 selects the depth group (from part b); L31-L23 + ME are compared against the fixed base-address pattern to gate the whole module's chip-selects; L21-L0, R/W!, and D0-D7 connect identically to both depth groups.

Fig. Q6(b)/(c): two width-expansion columns (4-bit chips forming 8-bit D0–D7) stacked into two depth groups, selected by the extra address bit A22 (decoded internally) and, for (c), gated by a fixed-pattern compare of L31–L23 against the base 0x10000000.

Final results — Question 6
Part	Result
(a)	$\boxed{2\ \text{MB}}$ ($2^{22}$ rows × 4 bits)
(b)	$\boxed{4\ \text{chips}}$ (2 width × 2 depth) + a 1-of-2 decoder on 1 extra address bit
(c)	L22 selects depth group; L31–L23+ME compared against the fixed `0x10000000` pattern gates the module; L21–L0/R-W!/D0–D7 shared

Topic: Memory-chip capacity sizing, width/depth expansion when composing chips into a larger module, and high-order address decoding to place a module at a fixed base address.

Key relations: rows $=2^{\#\text{address lines}}$; capacity (bits) $=$ rows $\times$ data width; width chips $=$ target width / chip width; depth groups $=\lceil$target bytes / (width-group capacity)$\rceil$; a module's chip-select compares only the address bits ABOVE its own internal offset width against a fixed base pattern.

Why this works: width and depth are orthogonal composition axes — wiring chips side-by-side widens the word without adding capacity per address, while wiring separate address-decoded groups adds capacity without widening the word; placing the composed module at an ARBITRARY base address only ever needs to examine the bits above the module's own internal address width, because every bit below that width is already fully consumed indexing WITHIN the module.

Common pitfall: forgetting the extra depth-select bit still needs its own (even if simple) decode logic; assuming the module's chip-select comparator must examine all 32 address bits rather than only the bits above its own internal offset width; treating a self-contradictory pin-count description as a single unambiguous number without flagging the assumption.

Source: Patterson & Hennessy, Computer Organization and Design, 6th ed., Ch.5 (memory technology, chip organization, width/depth expansion, memory-mapped address decoding).

Question 6 of 6

Question 6 (20 marks)