Paper format. National Exams, December 2014 — 07-Elec-A4,
Digital Systems & Computers. Three hours, closed book
(one approved Casio or Sharp calculator). Six questions, each worth 12 marks;
the rubric states that five questions constitute a complete paper.
A table of Boolean identities and a flip-flop excitation table are supplied with
the paper. All six questions are solved below, because this set is
intended as a study resource rather than a timed attempt.
Reference texts.
- M. Morris Mano and M. D. Ciletti, Digital Design, 6th ed. —
Boolean minimisation (Ch. 3), combinational building blocks (Ch. 4),
synchronous sequential logic (Ch. 5), programmable logic (Ch. 7).
- J. F. Wakerly, Digital Design: Principles and Practices, 5th ed.
— hazards and glitch-free design (Ch. 3), decoders and multiplexers
(Ch. 6), PLA/PAL architectures (Ch. 6).
- C. Hamacher, Z. Vranesic, S. Zaky and N. Manjikian, Computer
Organization and Embedded Systems, 6th ed. — address decoding,
programmed vs. interrupt-driven I/O, parallel-interface handshaking
(Ch. 3 and Ch. 4).
Check: Question 4 figure. The AND-plane and OR-plane wiring of the Q4 circuit is read from the printed figure. The four product terms and the two OR gates are unambiguous, and the upper OR gate clearly drives RA. One detail of the printed figure is genuinely ambiguous: the lower OR gate's output wire runs at almost exactly the same height as
the feedback rails returning from flip-flop B, so it cannot be resolved with
certainty whether it lands on RB (the reading used below, which yields a well-formed machine) or on SA. The solution below states the wiring it
assumes explicitly, and Question 4 closes with the alternative reading and its
consequence so that either version can be reproduced.
