HC11 address decoding and I/O routing (12 marks): 22-Elec-A4 Digital Systems and Computers, December 2014, Q5

Question 5: HC11 address decoding and I/O routing (12 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. The routing hardware shown below, and four two- instruction sequences to classify.

The PD0 routing hardware: a page decode clocks a D flip-flop whose Q and Q' drive the two digital switches.

Given data — decoding hardware
Item	Value
Decoder address inputs	$A_2 A_1 A_0 = A_{15} A_{14} A_{13}$
Flip-flop clock	$\overline{Y}_0$ of the decoder (rising edge as it returns to 1)
Flip-flop data input	HC11 data bus line $D_4$
Switch 1 control	$C_1 = Q$ — closed routes $PD_0$ to the HOST port
Switch 2 control	$C_2 = \overline{Q}$ — closed routes $PD_0$ to the MCU port
Decoder page size	$2^{13} = 8192$ bytes (8 KiB) per output

Find. For each of the four instruction pairs, whether it routes $PD_0$ to the HOST port, to the MCU port, or leaves the current routing untouched — with justification.

Approach. Two independent conditions must both be met before the routing can change: the bus cycle must fall inside the address page that asserts $\overline{Y}_0$, and it must be a write cycle that puts the intended bit on $D_4$. Establish the address page for each instruction first, then examine $D_4$ only for those that survive.

Find the address range that clocks the flip-flop. The decoder sees only the top three address bits, so it splits the HC11's 64 KiB space into eight equal pages: $$\text{page size} = 2^{16-3} = 2^{13} = 8192 \text{ bytes}$$ Output $\overline{Y}_0$ is asserted when $A_{15}A_{14}A_{13} = 000$, that is for $$\boxed{\text{addresses } \mathtt{0000_{16}} \text{ to } \mathtt{1FFF_{16}}}$$ Every other address activates a different output and leaves $\overline{Y}_0$ high, so no clock edge is produced.
Note what actually produces the edge. The question states that all active-low outputs return to '1' at the end of the instruction cycle. The flip-flop therefore captures $D_4$ on the rising edge of $\overline{Y}_0$, at the end of a cycle that addressed page 0. This matters because the data bus must still be carrying the operand at that instant — which is true for a store, and not meaningfully true for a load.

The 64 KiB space split into eight 8 KiB decoder pages, with the four instruction addresses placed. Only (b) falls in the Y0' page.

(a) ldaa #$21, staa $2B00 (3 marks). The store targets address $\mathtt{2B00_{16}}$, whose top three bits are $$\mathtt{2B00_{16}} = 0010\,1011\,0000\,0000_2 \Rightarrow A_{15}A_{14}A_{13} = 001$$ This asserts $\overline{Y}_1$, not $\overline{Y}_0$. The flip-flop is never clocked, so $$\boxed{\text{(a) No Action}}$$ The data value $\mathtt{21_{16}}$ (whose $D_4$ happens to be 0) is irrelevant, because it is never captured.
(b) ldaa #$FF, staa $10F0 (3 marks). The store targets $$\mathtt{10F0_{16}} = 0001\,0000\,1111\,0000_2 \Rightarrow A_{15}A_{14}A_{13} = 000$$ which lies inside page 0, so $\overline{Y}_0$ is asserted and its return to '1' clocks the flip-flop. The byte on the data bus is $\mathtt{FF_{16}}$, all ones, so $D_4 = 1$ and the flip-flop captures $Q = 1$. That closes switch 1 ($C_1 = Q = 1$) and opens switch 2 ($C_2 = \overline{Q} = 0$): $$\boxed{\text{(b) HOST Computer I/O port}}$$
(c) ldaa #$90, staa $3000 (3 marks). The store targets $$\mathtt{3000_{16}} = 0011\,0000\,0000\,0000_2 \Rightarrow A_{15}A_{14}A_{13} = 001$$ again page 1, asserting $\overline{Y}_1$. No clock edge reaches the flip-flop: $$\boxed{\text{(c) No Action}}$$ This part is the deliberate trap of the question: the data byte $\mathtt{90_{16}} = 1001\,0000_2$ does have $D_4 = 1$, so a candidate who checks only the data and not the address will wrongly answer "HOST". The address decode is what gates everything.
(d) ldaa #$8D, ldaa $2FFF (3 marks). This pair fails on both counts. The second instruction is a load, not a store: it reads from memory rather than driving the data bus with a value to be captured. And its address is $$\mathtt{2FFF_{16}} = 0010\,1111\,1111\,1111_2 \Rightarrow A_{15}A_{14}A_{13} = 001$$ which is page 1 in any case. Either reason alone is sufficient: $$\boxed{\text{(d) No Action}}$$
Collect the result. Only instruction pair (b) changes the routing, sending $PD_0$ to the HOST computer port. The other three leave whatever routing was previously latched completely untouched — which is the point of using a flip-flop rather than combinational decoding: the selection persists until it is deliberately rewritten.

Check: no instruction in this set selects the MCU port. Working the decode strictly as specified, three of the four pairs miss the $\overline{Y}_0$ page entirely and the one that hits it carries $D_4 = 1$, so the MCU I/O port is never selected by this particular list. That is a consistent and defensible answer — the question asks which instructions do each of the three things, and "none" is a valid entry for one column. To route $PD_0$ to the MCU port one would store any byte with $D_4 = 0$ into page 0, for example ldaa #$0F followed by staa $1000.

Question 5 — final results
Instruction pair	Address page	Decoder output	$D_4$	Routing
(a) `staa $2B00`	001	$\overline{Y}_1$	not captured	No Action
(b) `staa $10F0`	000	$\overline{Y}_0$	1	HOST Computer I/O port
(c) `staa $3000`	001	$\overline{Y}_1$	not captured	No Action
(d) `ldaa $2FFF`	001	$\overline{Y}_1$	load, not store	No Action
$\overline{Y}_0$ page spans $\mathtt{0000_{16}}$–$\mathtt{1FFF_{16}}$ (8 KiB)

Topic. Partial address decoding and memory-mapped output ports in a microcontroller system.

Key relations. Decoding the top k address bits of an n-bit address space produces $2^k$ pages of $2^{n-k}$ bytes each. Here $n = 16$, $k = 3$, giving eight pages of 8 KiB. A memory-mapped output port is a register clocked by the coincidence of an address decode and a write strobe, so its content persists until the next write to the same address.

Why this works. Because only $A_{15}$–$A_{13}$ are decoded, every address within a page is equivalent as far as the hardware is concerned: $\mathtt{10F0_{16}}$, $\mathtt{0000_{16}}$ and $\mathtt{1FFF_{16}}$ all select $\overline{Y}_0$. This is partial decoding, and it is deliberate — it trades away address space (the port responds to 8192 different addresses, an effect known as aliasing or foldback) in exchange for a much simpler and faster decoder. Latching on the trailing edge of the decode is the standard way to guarantee that the data bus has settled before it is captured.

Common pitfall. Checking the data byte before checking the address, which makes part (c) look like a HOST selection. The decode gates everything, so the address must be resolved first. The second trap is treating a ldaa from an address the same as a staa to it: a read cycle does not drive the processor's data on the bus, so nothing meaningful is latched even if the address decodes correctly. In real 68HC11 hardware the write strobe would additionally be qualified by the R/W line and the E clock.

Source. Hamacher, Vranesic, Zaky & Manjikian, Computer Organization and Embedded Systems 6th ed., §3.1–3.3 (accessing I/O devices, memory-mapped I/O, address decoding); Mano & Ciletti, Digital Design 6th ed., §4.9 (decoders and their use in address selection).

Question 5 of 6: HC11 address decoding and I/O routing (12 marks)

Question 5: HC11 address decoding and I/O routing (12 marks)