Question 3 of 6: Four-output minimisation and PLA implementation (12 marks)

Question 3: Four-output minimisation and PLA implementation (12 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A three-input, four-output truth table, reproduced below exactly as printed in the paper.

Find. A minimal two-level expression for each of the four outputs via Karnaugh maps, and a PLA realisation of all four together.

Approach. Read each output column off the table as a minterm list, minimise it on its own three-variable map, and then — because a PLA shares one AND plane across all outputs — count the distinct product terms across the four expressions to size the array.

(a) Minimisation by K-map (6 marks)

1. Extract the four ON-sets. Reading each output column down the table and recording the row indices where it is 1: $$X = \sum m(2,6,7) \qquad Y = \sum m(0,1,3,5,6,7)$$ $$Z = \sum m(0,1,5) \qquad W = \sum m(0,1,2,3,5,6)$$

Each column is now mapped and looped independently.

1. Read the loops off the four maps. Each loop of $2^k$ cells eliminates k variables, giving $$X = \boxed{AB + B\overline{C}} \qquad Y = \boxed{\overline{A}\,\overline{B} + AB + C}$$ $$Z = \boxed{\overline{A}\,\overline{B} + \overline{B}C} \qquad W = \boxed{\overline{A} + \overline{B}C + B\overline{C}}$$ Note the four-cell loop in Y covering all of column $C = 1$, which reduces to the single literal C, and the four-cell loop in W covering the whole $A = 0$ row, which reduces to $\overline{A}$.
2. Confirm against the table. Each expression was evaluated at all eight input combinations and matched to its column; for example $W$ at $ABC = 111$ gives $\overline{A} = 0$, $\overline{B}C = 0$ and $B\overline{C} = 0$, so $W = 0$, agreeing with the last row.

(b) PLA implementation (6 marks)

1. Collect the distinct product terms. The four minimal expressions between them name ten product-term instances, but several terms appear in more than one output. Listing them without repetition: $$\overline{A},\quad \overline{A}\,\overline{B},\quad AB,\quad B\overline{C},\quad \overline{B}C,\quad C$$ which is $\boxed{6\text{ distinct product terms}}$.
2. Quantify the sharing. Four of the six terms are used twice — $\overline{A}\,\overline{B}$ by Y and Z, $AB$ by X and Y, $B\overline{C}$ by X and W, and $\overline{B}C$ by Z and W. The array therefore serves $$10 \text{ term instances with } 6 \text{ AND rows} \;\Rightarrow\; \boxed{4 \text{ rows saved}}$$
3. Size the array. The PLA needs three inputs (each available true and complemented), six product rows and four outputs: $$\boxed{3 \times 6 \times 4 \text{ PLA}}$$ The programming map below shows which literals enter each product (AND plane) and which products are summed into each output (OR plane).

This heavy sharing is exactly the case a PLA is designed for. In a PAL, the OR plane is fixed and each output owns a private group of AND rows, so the same design would need all ten product terms — the four shared terms would have to be duplicated. The PLA's programmable OR plane lets one physical AND row drive two outputs, so the sharing translates directly into a 40 % smaller array. Where a design shows little or no sharing the argument reverses and the simpler, faster PAL is preferred.