Question 4 of 6: RS flip-flop finite state machine (12 marks)

Question 4: RS flip-flop finite state machine (12 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A clocked sequential circuit with one external input X, a common clock, an AND–OR combinational block, and two RS flip-flops whose outputs are labelled A and B. Both true and complemented outputs are fed back into the AND plane.

Find. The four excitation equations, the state transition table, the state transition diagram, and an assessment of whether JK flip-flops would improve the design.

Approach. Read the four AND-plane product terms off the figure, combine them through the two OR gates to get the excitation equations, then drive the RS characteristic behaviour over all eight (state, input) combinations to build the transition table, from which the diagram follows directly.

(a) Excitation equations (3 marks)

1. Read the four product terms. Each 3-input AND gate takes one literal from the X pair and one from each feedback pair: $$P_1 = \overline{X}AB \qquad P_2 = X\overline{A}\,\overline{B} \qquad P_3 = \overline{X}A\overline{B} \qquad P_4 = XA\overline{B}$$
2. Combine through the OR plane. The upper OR gate collects $P_1$ and $P_2$ into $R_A$; $S_A$ is taken directly from $P_4$; the lower OR gate collects $P_3$ and $P_4$ into $R_B$; and $S_B$ is taken directly from $P_2$: $$\boxed{R_A = \overline{X}AB + X\overline{A}\,\overline{B}} \qquad \boxed{S_A = XA\overline{B}}$$ $$\boxed{R_B = \overline{X}A\overline{B} + XA\overline{B} = A\overline{B}} \qquad \boxed{S_B = X\overline{A}\,\overline{B}}$$
3. Note the simplification in $R_B$. The two terms feeding the lower OR gate differ only in the X literal, so $\overline{X}A\overline{B} + XA\overline{B} = A\overline{B}(\overline{X} + X) = A\overline{B}$. The gate is genuinely redundant: B is reset whenever the machine is in a state with $A = 1, B = 0$, irrespective of the input.
4. Check the forbidden condition. An RS flip-flop must never see $R = S = 1$. For flip-flop A, every term of $R_A$ contains either $\overline{X}$ or $\overline{A}$ while $S_A$ requires $X$ and $A$, so the two can never be asserted together. For flip-flop B, $R_B$ requires $A = 1$ while $S_B$ requires $\overline{A}$. The design is therefore well formed at every input combination.

(b) State transition table (4 marks)

The RS characteristic behaviour is: assert S to set, assert R to reset, and hold when both are 0. Evaluating the four equations at each of the eight combinations of present state $AB$ and input X, then applying that rule to each flip-flop independently:

Two rows deserve comment. At $AB = 00$, $X = 1$ the term $P_2 = X\overline{A}\,\overline{B}$ fires and drives both $R_A$ and $S_B$, so the machine moves to 01 — A is reset (it was already 0, so this has no visible effect) while B is set. At $AB = 11$, $X = 0$ the term $P_1 = \overline{X}AB$ asserts $R_A$ alone, taking the machine from 11 to 01.

(c) State transition diagram (2 marks)

1. Identify the absorbing states. State 01 maps to itself for both values of X, because with $A = 0$ every product term is dead ($P_1$ needs $B$ and $A$; $P_2$, $P_3$, $P_4$ all need $\overline{B}$ or $A$). State 10 is likewise a trap: $R_B = A\overline{B} = 1$ holds B reset while $S_A$ holds A set. Once entered, neither state is ever left: $$\boxed{01 \text{ and } 10 \text{ are absorbing states}}$$
2. Trace the behaviour from reset. Starting from $AB = 00$, the machine idles while $X = 0$ and moves to 01 on the first $X = 1$, where it remains permanently. States 10 and 11 are therefore unreachable from the 00 reset state; they can only be entered if the flip-flops power up in one of them. From 11 the machine falls to 01 on $X = 0$ and holds on $X = 1$; from 10 it never escapes.

As a design this is degenerate — a machine that latches into 01 after one input pulse and stays there is a one-shot, not a counter or a sequencer. That is a legitimate observation to record: the marks are for extracting the behaviour correctly, and the correct behaviour here is a machine with two absorbing states and only two reachable states from reset.

(d) Would JK flip-flops help? (3 marks)

The JK flip-flop is the RS flip-flop with the forbidden input combination redefined rather than outlawed. Writing the two characteristic equations side by side,

Setting $J = S$ and $K = R$ makes the two devices behave identically at every input combination that is legal for the RS flip-flop; the difference appears only at $J = K = 1$, where the JK toggles instead of producing an indeterminate output. So the JK is a strict functional superset of the RS.

1. The immediate advantage: the design constraint disappears. With RS flip-flops the designer must prove that $R$ and $S$ are never asserted together — the check carried out in part (a). With JK flip-flops that obligation vanishes, because every input combination is defined. The excitation table gains a don't-care in every row (each JK entry is either $0/\times$ or $\times/1$ where the RS entry is a fixed 0 or 1), and don't-cares are exactly what makes K-map minimisation produce smaller equations.
2. The advantage for this particular circuit. Substituting $J_A = S_A$, $K_A = R_A$, $J_B = S_B$, $K_B = R_B$ reproduces this machine immediately, so nothing is lost. The extra freedom would allow the excitation logic to be re-minimised with the new don't-cares — and because a JK also toggles, states such as the 10 trap could be broken with a single $J = K = 1$ term rather than a separate set and reset path. For a machine with this few product terms the saving is small, but the direction of the trade is always favourable.
3. The cost. A JK flip-flop is marginally larger than an RS flip-flop, and the master–slave or edge-triggered structure needed to avoid the "racing" that a level-sensitive JK suffers when $J = K = 1$ adds a little more. Since the circuit is already clocked and edge-triggered, that cost is already being paid here.

Conclusion. Yes, there is an advantage, and it is one of design freedom rather than of function: the JK realises everything the RS can, removes the $R = S = 1$ prohibition that must otherwise be verified by hand, and supplies extra don't-cares that generally yield simpler and cheaper excitation logic. No RS-based design can do anything a JK-based design cannot.