Question 2 of 6: 3-bit synchronous counter with a count-enable input

Question 2 (12 marks) — 3-bit synchronous counter with a count-enable input

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Three positive-edge-triggered JK flip-flops, the full mod-8 binary sequence 000 through 111, bit weights $Q_{C}Q_{B}Q_{A}$ with $Q_{A}$ the least significant, and in part (b) one extra level input CTE.

Find. (a) the J and K excitation equations and the counter schematic, and (b) the modification that freezes and resumes the count under CTE control.

Approach. Use the JK toggle property rather than a 24-row excitation table: in a straight binary up-count, bit $n$ toggles on exactly those clocks where every lower bit is 1, so each stage needs $J=K$ tied to the AND of the lower $Q$ outputs.

1. Recall the JK excitation shorthand. With $J=K=1$ a JK flip-flop toggles on the active edge; with $J=K=0$ it holds. So for any counter whose next state differs from the present state only by toggling, the required excitation is simply $$J_{X} = K_{X} = T_{X} = Q_{X}\oplus Q_{X}^{+}$$ and the whole design reduces to deciding when each bit toggles.
2. Find the toggle condition for each bit. In a binary up-count a bit flips when the carry propagates into it, that is when all less significant bits are 1. Reading the required sequence 000, 001, ..., 111: $Q_{A}$ flips on every clock; $Q_{B}$ flips whenever $Q_{A}=1$ (at 001, 011, 101, 111); and $Q_{C}$ flips whenever $Q_{A}=Q_{B}=1$ (at 011 and 111). Hence$$\boxed{\,J_{A}=K_{A}=1,\qquad J_{B}=K_{B}=Q_{A},\qquad J_{C}=K_{C}=Q_{A}\cdot Q_{B}\,}$$
3. (a) Draw the synchronous counter. All three clock inputs are tied to the same CLK line — that is what makes the counter synchronous — and the only combinational hardware is a single two-input AND gate.
   Q2(a) 3-bit synchronous binary up counter. One AND gate is the entire combinational network.
   Because all three flip-flops see the same edge, every output settles within one clock-to-Q delay of that edge, so the counter has no ripple skew and a maximum frequency set by $t_{CQ}+t_{AND}+t_{su}$ rather than by the number of stages.
4. (b) Add COUNT ENABLE the correct way. The one thing not to do is gate the clock: inserting a gate in the CLK path adds skew, and a CTE change near an edge can produce a runt pulse that clocks some flip-flops and not others. Instead AND CTE into every J and K input, so that CTE = 0 forces every stage into its hold state:$$J_{A}=K_{A}=\mathrm{CTE},\qquad J_{B}=K_{B}=Q_{A}\cdot\mathrm{CTE},\qquad J_{C}=K_{C}=Q_{A}\cdot Q_{B}\cdot\mathrm{CTE}$$
   Q2(b) the same counter with CTE gating only the J and K inputs; the clock path is untouched.
   With CTE = 0 all six excitation inputs are 0, every flip-flop holds, and the clock keeps running harmlessly. When CTE returns HIGH the stored state is untouched, so counting resumes from exactly where it stopped — which is precisely the behaviour the question specifies. The cost is one extra AND input on stages B and C plus one two-input AND for stage A.