Question 5 of 6: Building a 64 Kbyte memory from 16K × 4 chips

Question 5 (16 marks) — Building a 64 Kbyte memory from 16K × 4 chips

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. An 8-bit CPU requiring a 64 Kbyte address space, and memory chips organised as 16K × 4.

Find. (a) the number of chips and the bus widths written into the figure, (b) the chip-select decoding logic with its Boolean expressions, and (c) the address range of each chip.

Approach. Size the array in two independent directions — width first (how many chips to make one byte) and then depth (how many such banks to fill the space) — then split the address bus into the low lines that go to every chip and the high lines that select between banks.

1. Expand the width. Each chip supplies only 4 of the 8 bits the CPU expects, so two chips must be operated in parallel on the same addresses, one carrying $D_{7}\ldots D_{4}$ and the other $D_{3}\ldots D_{0}$:$$\text{chips per bank} = \frac{w}{w_{c}} = \frac{8}{4} = 2$$ Both chips of a pair share one chip-select signal, because they are two halves of the same byte and must always be enabled together.
2. Expand the depth. A bank of two chips holds 16K bytes, so the number of banks needed is$$\text{banks} = \frac{N}{n_{c}} = \frac{65\,536}{16\,384} = 4 \qquad\Rightarrow\qquad \boxed{\;4\ \text{banks}\times 2\ \text{chips} = 8\ \text{chips total}\;}$$ This is why the printed figure is drawn as columns of two with the buses continuing off to the right.
3. (a) Split the address bus and fill in the numbers. Addressing 16K words inside a chip needs $\log_{2}(16\,384) = 14$ address lines, and the full 64 Kbyte space needs $\log_{2}(65\,536) = 16$. The difference is the bank selector:$$16 - 14 = 2 \ \text{lines} \;(A_{15}, A_{14}) \ \text{select the bank};\qquad A_{13}\ldots A_{0}\ \text{go to every chip}$$

   Q5(a) numbers written into the figure

   Blank	Value
   Address bus width	16 ($A_{15}-A_{0}$)
   Data bus width	8 ($D_{7}-D_{0}$)
   Address lines to each chip	14 ($A_{13}-A_{0}$)
   Data lines, upper chip of each pair	4 ($D_{7}-D_{4}$)
   Data lines, lower chip of each pair	4 ($D_{3}-D_{0}$)
   Number of chips	8 (4 banks × 2)

4. (b) Derive the chip-select logic. Bank $k$ must be enabled exactly when $A_{15}A_{14}$ equals the binary code of $k$. The selects are active low, so each is 0 for one code and 1 otherwise — which is precisely an OR gate fed with the appropriate polarities, since an OR output is low only when both inputs are low:$$\overline{CS}_{0} = A_{15}+A_{14},\qquad \overline{CS}_{1} = A_{15}+\overline{A_{14}},\qquad \overline{CS}_{2} = \overline{A_{15}}+A_{14},\qquad \overline{CS}_{3} = \overline{A_{15}}+\overline{A_{14}}$$ Each expression is the De Morgan dual of the AND-form minterm $\overline{CS}_{k} = \overline{m_{k}(A_{15},A_{14})}$, so the four together are simply a 2:4 decoder with active-low outputs — a single 74138-style part could replace the four gates.
   Q5 completed memory system: four banks of two 16K × 4 chips, with one OR gate per bank generating the active-low chip select.
   The connections follow from the sizing: $A_{13}\ldots A_{0}$ run to all eight chips in parallel, the upper chip of each pair drives $D_{7}-D_{4}$ and the lower drives $D_{3}-D_{0}$, and the two chips of a bank share the one $\overline{CS}$. Because exactly one of the four expressions is low for any $A_{15}A_{14}$ combination, only one bank ever drives the data bus and there is no contention.
5. (c) Work out the address ranges. Bank $k$ occupies the addresses whose top two bits are $k$ and whose low 14 bits run over the full chip:$$\text{bank } k:\quad k\cdot 2^{14} \ \text{to}\ (k+1)\cdot 2^{14}-1 = k\cdot 16\,384 \ \text{to}\ k\cdot 16\,384 + 16\,383$$

   Q5(c) address allocation

   Bank	$A_{15}A_{14}$	Chips	Address range	Size
   0	00	chips 1 & 2	$\mathtt{0000}_{16}$ – $\mathtt{3FFF}_{16}$	16K
   1	01	chips 3 & 4	$\mathtt{4000}_{16}$ – $\mathtt{7FFF}_{16}$	16K
   2	10	chips 5 & 6	$\mathtt{8000}_{16}$ – $\mathtt{BFFF}_{16}$	16K
   3	11	chips 7 & 8	$\mathtt{C000}_{16}$ – $\mathtt{FFFF}_{16}$	16K

   The four ranges tile the space exactly: they start at $\mathtt{0000}_{16}$, finish at $\mathtt{FFFF}_{16}$, and each begins one address after the previous one ends, so there is neither a hole nor an overlap in the 64 Kbyte map. Note that both chips of a bank share the same range — they are split across the data bus, not across the address space.