Question 4 of 6: Address decoding and I/O routing on an HC11 system

Question 4 (12 marks) — Address decoding and I/O routing on an HC11 system

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. The routing network on page 5 of the paper. The decoder takes $A_{2}A_{1}A_{0} = A_{15}A_{14}A_{13}$; only $\overline{Y_{2}}$ is wired, and it drives the flip-flop clock; the flip-flop D input is data-bus line $D_{0}$; $Q$ closes digital switch 1 to the HOST port and $\overline{Q}$ closes digital switch 2 to the MCU port. Four instruction pairs are to be classified.

Find. For each of (a) to (d), whether PD0 is routed to the HOST port, to the MCU port, or left unchanged, with the justification.

[Figure not reproduced: Q4 routing network redrawn from page 5. Only $\overline{Y_{2}}$ leaves the decoder, so only one address block can ever clock the flip-flop. See the official exam paper.]

Approach. Each instruction pair does two independent things: the address in the staa decides whether the flip-flop is clocked at all, and the data in the ldaa decides what gets latched. Test the address first — if the decoder does not select $\overline{Y_{2}}$, the data is irrelevant.

1. Find the address block that the decoder recognises. The decoder asserts $\overline{Y_{2}}$ (the only output that is wired) when its inputs read $A_{2}A_{1}A_{0} = 010$, that is when $A_{15}A_{14}A_{13} = 010$. The remaining thirteen address lines are not decoded, so the whole $2^{13}$-byte block responds:$$\text{block} = 010\underbrace{\,x\ldots x\,}_{13\ \text{bits}} \;\Rightarrow\; \boxed{\;\mathtt{4000}_{16}\ \text{to}\ \mathtt{5FFF}_{16}\;}$$ Only a staa whose destination falls inside that range can affect the routing.
2. Establish which edge does the latching. The question states that at the end of each instruction cycle all active-low decoder outputs return to logic 1. So during a store to the selected block, $\overline{Y_{2}}$ falls to 0 and then rises again — and it is that rising edge at the end of the cycle that clocks the flip-flop, capturing whatever the CPU is driving on $D_{0}$. The value latched is therefore the least significant bit of the accumulator, $D_{0} = \mathrm{bit}_{0}$ of the ldaa operand.
3. Translate a latched bit into a routing decision. Switch 1 is controlled by $Q$ and switch 2 by $\overline{Q}$, and a switch closes on a logic 1. The two are therefore complementary and exactly one path is ever closed:$$Q = D_{0} = 1 \Rightarrow \text{HOST port},\qquad Q = D_{0} = 0 \Rightarrow \text{MCU port}$$
4. Apply the two tests to each instruction pair. Taking the top three address bits of each destination and the bottom bit of each operand:

   Q4 case-by-case evaluation

   Case	Destination	$A_{15}A_{14}A_{13}$	Decoder line	Operand	$D_{0}$	Result
   (a)	$8000	100	$\overline{Y_{4}}$ — not wired	$10 = 0001 0000	0	No action
   (b)	$4000	010	$\overline{Y_{2}}$ — selected	$29 = 0010 1001	1	HOST computer I/O port
   (c)	$5000	010	$\overline{Y_{2}}$ — selected	$B4 = 1011 0100	0	MCU I/O port
   (d)	$2500	001	$\overline{Y_{1}}$ — not wired	$05 = 0000 0101	1	No action

   Cases (a) and (d) are the instructive ones. Both write a perfectly valid data value — and (d) even writes a 1 in bit 0, which would have selected the HOST port — but neither address decodes to $\overline{Y_{2}}$, so the flip-flop is never clocked and the previous routing survives untouched. Case (c) also shows that any address in the block works: $5000 and $4000 are different addresses but the same decoded block, because $A_{12}$ downwards are ignored.