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22-Elec-A4 Digital Systems and Computers: May 2017

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

  1. Question 1 Boolean minimisation, K-map verification and hazard removal
  2. Question 2 Synchronous counter design with D flip-flops
  3. Question 3 2-bit adder outputs by K-map, implemented in a PAL
  4. Question 4 FSM built from an 8:1 MUX, a T and a D flip-flop
  5. Question 5 Parallel I/O — CPU polling vs interrupts, and handshake protocols
  6. Question 6 68HC11 parallel-port address decoding, read strobes and handshake timing

Start with Question 1 →

Paper format. National Exams, May 2017 — 16-Elec-A4 Digital Systems & Computers. Three hours, closed book, one approved Casio or Sharp calculator. Six questions, each worth 12 points; any five constitute a complete exam. A flip-flop excitation table and a list of Boolean identities are printed on the last page. Every one of the six questions is solved below, because the set is intended as a study resource rather than an exam script.

Reference texts. M. Morris Mano & M. D. Ciletti, Digital Design (6th ed.), ch. 3 (map simplification, prime implicants, hazards), ch. 4–5 (combinational and sequential design), ch. 6 (counters); J. F. Wakerly, Digital Design: Principles and Practices (5th ed.), §4.4 (timing hazards and consensus terms), ch. 7 (sequential-circuit design); C. Hamacher, Z. Vranesic, S. Zaky & N. Manjikian, Computer Organization and Embedded Systems (6th ed.), ch. 3 (memory-mapped I/O, program-controlled and interrupt I/O); F. M. Cady, Software and Hardware Engineering: Motorola M68HC11, ch. 8–9 (parallel I/O and handshaking).