22-Elec-A4 Digital Systems and Computers · May 2017

Question 2 of 6: Synchronous counter design with D flip-flops

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams, May 2017 — 16-Elec-A4 Digital Systems & Computers. Three hours, closed book, one approved Casio or Sharp calculator. Six questions, each worth 12 points; any five constitute a complete exam. A flip-flop excitation table and a list of Boolean identities are printed on the last page. Every one of the six questions is solved below, because the set is intended as a study resource rather than an exam script.

Reference texts. M. Morris Mano & M. D. Ciletti, Digital Design (6th ed.), ch. 3 (map simplification, prime implicants, hazards), ch. 4–5 (combinational and sequential design), ch. 6 (counters); J. F. Wakerly, Digital Design: Principles and Practices (5th ed.), §4.4 (timing hazards and consensus terms), ch. 7 (sequential-circuit design); C. Hamacher, Z. Vranesic, S. Zaky & N. Manjikian, Computer Organization and Embedded Systems (6th ed.), ch. 3 (memory-mapped I/O, program-controlled and interrupt I/O); F. M. Cady, Software and Hardware Engineering: Motorola M68HC11, ch. 8–9 (parallel I/O and handshaking).

Question 2: Synchronous counter design with D flip-flops (12 points)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A synchronous 3-bit counter with state variables Q_A (MSB), Q_B, Q_C (LSB), cycling through the six states 000 → 001 → 011 → 100 → 110 → 111 → 000. The two states 010 and 101 are unused. Implementation is with D flip-flops, whose characteristic is simply $Q^+ = D$.

Find. The three D input equations (with the unused states treated as don't-cares), the output timing diagram, and whether the resulting circuit is self-starting.

Approach. Because $Q^+ = D$ for a D flip-flop, the excitation table is the next-state table — tabulate each present state's successor, K-map each next-state bit with 010/101 as don't-cares, then feed the two unused states back through the finished equations to decide self-start.

Fig Q2.1 — Datapath: three D flip-flops clocked in common, each fed by its minimised excitation equation.

Part (a): build the state / excitation table. Listing each present state and its specified successor, and using $D_i = Q_i^+$:

Next-state table (D_A=Q_A⁺, D_B=Q_B⁺, D_C=Q_C⁺)
Q_A Q_B Q_C	Q_A⁺ Q_B⁺ Q_C⁺	D_A D_B D_C
0 0 0	0 0 1	0 0 1
0 0 1	0 1 1	0 1 1
0 1 1	1 0 0	1 0 0
1 0 0	1 1 0	1 1 0
1 1 0	1 1 1	1 1 1
1 1 1	0 0 0	0 0 0
0 1 0, 1 0 1	unused — don't-care (X)

K-map each excitation bit. Grouping the 1-cells with 010 and 101 available as don't-cares gives three compact two-term expressions: $$\boxed{D_A = Q_A\bar Q_C + \bar Q_A Q_B}$$ $$\boxed{D_B = Q_A\bar Q_C + \bar Q_B Q_C}$$ $$\boxed{D_C = Q_B\bar Q_C + \bar Q_A \bar Q_B}$$ Substituting every one of the six specified states back into these equations reproduces the required successor exactly, so part (a) is complete: three D flip-flops, six 2-input AND gates and three OR gates.
Part (b): timing diagram. Sampling the state on each rising clock edge and walking the sequence, Q_A is low for the first three states and high for the last three; Q_B follows the pattern 0,0,1,0,1,1; Q_C follows 0,1,1,0,0,1. The waveform below shows seven clock cycles, so the sequence visibly repeats after six.

Fig Q2.2 — Output waveforms, sampled on the rising edge of CLK; the pattern repeats every six clocks.

Part (c): self-start test. Self-start is decided by the don't-care assignment the minimisation happened to make, so it must be read out of the finished equations, not from the specification. Feeding the two unused states through $D_A, D_B, D_C$: $$010 \;\longrightarrow\; 101, \qquad 101 \;\longrightarrow\; 010$$ The two unused states map onto each other, forming a closed two-state lock-out cycle that never enters the main sequence.
Conclusion on self-start. Because a power-up landing on 010 or 101 traps the counter in the 010↔101 loop forever, the design is $$\boxed{\text{NOT self-starting — an initial reset is required}}$$ The economical fix is to tie the flip-flops' clear (or preset) inputs to a power-on-reset pulse so the counter always begins inside the valid sequence.

Question 2 — final results
Quantity	Result
D_A	Q_AQ_C′ + Q_A′Q_B
D_B	Q_AQ_C′ + Q_B′Q_C
D_C	Q_BQ_C′ + Q_A′Q_B′
Unused-state behaviour	010 → 101 → 010 (2-state lock-out)
Self-starting?	No — initial reset required

Topic. Standard synchronous counter (finite-state-machine) design with D flip-flops, and self-start analysis of unused states.

Key relations. D flip-flop characteristic $Q^+ = D$, so the excitation equations equal the next-state equations; K-map minimisation with unused states as don't-cares; self-start decided by evaluating the minimised next-state equations on every unused state.

Why this works. The D flip-flop is the simplest to design with precisely because no excitation table lookup is needed — whatever next state the sequence demands is copied straight to D. Treating the unused states as don't-cares yields the cheapest gates, but it also silently assigns those states a next state; the designer does not get to choose it, the minimisation does. Reading it back is therefore mandatory: here the don't-cares happened to close 010 and 101 into a two-state ring disjoint from the main cycle, which is exactly the situation that makes a counter hang on power-up.

Common pitfall. Declaring the counter self-starting because “the unused states aren't in the sequence” — that reasoning inspects the specification, not the built circuit. Always substitute each unused state into the final equations; a counter is self-starting only if every unused state eventually flows into the valid cycle.

Source. Mano & Ciletti, Digital Design 6th ed., §5.7–5.8 (state-reduction and design procedure) and §6.4 (synchronous counters); Wakerly, Digital Design 5th ed., §7.4 (sequential-circuit design and unused states).

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