22-Elec-A4 Digital Systems and Computers · May 2017

Question 5 of 6: Parallel I/O — CPU polling vs interrupts, and handshake protocols

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Question 5: Parallel I/O — CPU polling vs interrupts, and handshake protocols (12 points)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A three-block parallel-I/O system — CPU ↔ I/O interface ↔ I/O device. The CPU–interface link carries Control signals, an IRQ line, and a bidirectional Data Bus; the interface–device link carries protocol signals H1 (interface→device) and H2 (device→interface) plus bidirectional Data Lines.

Find. (a) the two CPU-to-interface synchronisation methods and which is more efficient; (b) two device-side handshake protocols, the input and output step sequences of each, and the roles of H1 and H2.

(a) Two CPU synchronisation methods. To learn that new data has arrived (input) or that the interface is ready to accept data (output), the CPU uses one of two programming techniques. The first is program-controlled polling (also called programmed or busy-wait I/O): the CPU repeatedly reads a status bit in the interface and loops until that bit signals “data ready” or “ready to accept,” then executes the transfer. The second is interrupt-driven I/O: the interface asserts the IRQ line when it needs service, the CPU finishes its current instruction, saves context, vectors to an interrupt-service routine that performs the transfer, and then resumes the interrupted program.

Which is more efficient. Interrupt-driven I/O is the more efficient method. Under polling the CPU is trapped in a tight status-reading loop, consuming essentially 100 % of its cycles waiting for a comparatively slow peripheral and doing no useful work; worse, if it polls too slowly it can miss data. With interrupts the CPU runs other tasks and is disturbed only at the instant the peripheral actually needs attention, so processor time scales with the true data rate rather than with the wait. Polling is simpler to code and can win only when the device is known to be fast and the CPU has nothing else to do; for a general system, interrupts dominate on throughput and responsiveness. (In high-bandwidth cases a third technique, DMA, removes the CPU from the byte-by-byte loop entirely, but the two methods the question asks for are polling and interrupts.)

(b)(i) Two parallel-I/O handshake protocols. Between the interface and the external device the data exchange is timed by a two-wire handshake using H1 and H2. The two standard forms are: the fully interlocked (two-way) handshake, in which every edge of one control line must be answered by an edge of the other before the sequence proceeds; and the strobe (pulsed) handshake, in which the data source emits a single fixed-width control pulse to mark valid data, without waiting for a matching reply. The interlocked form is self-timing and robust to arbitrary device speed; the strobed form is faster and simpler but assumes the receiver is quick enough to capture the data during the pulse.

(b)(ii) Step sequences, and the roles of H1 and H2. In both directions H1 carries VALID DATA (asserted by whichever unit is sourcing the data) and H2 carries ACKNOWLEDGEMENT (asserted by whichever unit is receiving it).

INPUT (device → interface). (1) The I/O device places a data word on the Data Lines. (2) The device asserts H1 = VALID, telling the interface the data is stable. (3) The interface latches the word and asserts H2 = ACK to confirm reception. (4) Seeing ACK, the device removes the data and negates H1; the interface then negates H2, and both are ready for the next word. The interface also sets its status bit / raises IRQ so the CPU can read the captured byte.

OUTPUT (interface → device). (1) The interface (having been given a byte by the CPU) drives the word onto the Data Lines. (2) The interface asserts H1 = VALID to announce stable data. (3) The device reads the word and asserts H2 = ACK to confirm it has taken the data. (4) The interface negates H1 (and may signal the CPU it can supply the next byte); the device negates H2, completing the cycle. Thus the source–of–data unit always owns H1 (VALID) and the destination unit always owns H2 (ACK), which is why the same two wires serve both transfer directions.