22-Elec-A4 Digital Systems and Computers · May 2017

Question 6 of 6: 68HC11 parallel-port address decoding, read strobes and handshake timing

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams, May 2017 — 16-Elec-A4 Digital Systems & Computers. Three hours, closed book, one approved Casio or Sharp calculator. Six questions, each worth 12 points; any five constitute a complete exam. A flip-flop excitation table and a list of Boolean identities are printed on the last page. Every one of the six questions is solved below, because the set is intended as a study resource rather than an exam script.

Reference texts. M. Morris Mano & M. D. Ciletti, Digital Design (6th ed.), ch. 3 (map simplification, prime implicants, hazards), ch. 4–5 (combinational and sequential design), ch. 6 (counters); J. F. Wakerly, Digital Design: Principles and Practices (5th ed.), §4.4 (timing hazards and consensus terms), ch. 7 (sequential-circuit design); C. Hamacher, Z. Vranesic, S. Zaky & N. Manjikian, Computer Organization and Embedded Systems (6th ed.), ch. 3 (memory-mapped I/O, program-controlled and interrupt I/O); F. M. Cady, Software and Hardware Engineering: Motorola M68HC11, ch. 8–9 (parallel I/O and handshaking).

Question 6: 68HC11 parallel-port address decoding, read strobes and handshake timing (12 points)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A 68HC11 with a demultiplexed 16-bit address bus A15–A0, a multiplexed data bus AD7–AD0, and R/W̅ and E control lines, driving a parallel port. The status register lives at $A000 and the data register at $A001; nothing outside $A000–$A7FF may respond. A keyboard supplies data to eight D flip-flops (Q7–Q0) behind tri-state buffers, and a single STATUS D flip-flop flags new data. E is high for half of each bus cycle; R/W̅ = 1 on a read.

Find. (a) decode expressions PSTATUS, PDATA confined to the block; (b) the read-strobe expressions RSTATUS, RPORT; (c) the completed schematic wiring; (d) the interlocked-handshake timing waveforms with cause/clear arrows.

Approach. Convert the two hex addresses to binary to find which address bits are fixed across the block, decode on only those bits (fewest lines), gate the two read strobes with R/W̅·E so each is active for half a cycle, then wire VALID as the flip-flop clock and RPORT as the status-clear, consistent with the interlocked handshake.

Part (a): find the fixed address bits. In binary, $\text{A000}_{16} = 1010\,0000\,0000\,0000$ and $\text{A7FF}_{16} = 1010\,0111\,1111\,1111$. Across the whole $A000–$A7FF block the top five bits are constant at A15…A11 = 10100, while A10–A1 vary freely and A0 selects status (0) versus data (1). Decoding on the five fixed bits plus A0 is the fewest-line partial decode that keeps every response inside the block: $$\boxed{\text{PSTATUS} = A_{15}\bar A_{14} A_{13}\bar A_{12}\bar A_{11}\,\bar A_{0}}$$ $$\boxed{\text{PDATA} = A_{15}\bar A_{14} A_{13}\bar A_{12}\bar A_{11}\,A_{0}}$$ PSTATUS asserts for every even address in the block (all aliasing to the status register) and PDATA for every odd address; nothing outside $A000–$A7FF can assert either, because any change in A15…A11 breaks the fixed pattern.
Part (b): read strobes, active for ½ E cycle. A read occurs when R/W̅ = 1, and the bus data are valid only while E is high — which is exactly half of each bus cycle. Gating the decodes with R/W̅ and E gives strobes that are high for that half-cycle window: $$\boxed{\text{RSTATUS} = \text{PSTATUS}\cdot (R/\bar W)\cdot E}$$ $$\boxed{\text{RPORT} = \text{PDATA}\cdot (R/\bar W)\cdot E}$$ RSTATUS enables the status buffer onto the bus; RPORT enables the eight data-register buffers. Because both are ANDed with E, they automatically fall when E falls, satisfying the ½-cycle requirement.
Part (c): complete the wiring. The keyboard's VALID line (H1) is connected to the common clock of the eight data-register D flip-flops, so a VALID edge latches the new keyboard byte into Q7–Q0 and simultaneously clocks the STATUS flip-flop (whose D is tied to +5 V) to load a 1 — announcing “new data available.” The interface's ACK line (H2) is driven back to the keyboard to acknowledge capture. RPORT enables the data buffers onto AD7–AD0 and is also routed to the active-low CLR̅ of the STATUS flip-flop, so that the CPU's read of the data register clears the status flag. RSTATUS enables the status buffer so the CPU can poll the flag. These connections are shown in the completed schematic below.

Fig Q6.1 — Completed parallel-port schematic: VALID (H1) clocks the data and status flip-flops; ACK (H2) returns to the keyboard; RSTATUS/RPORT enable the tri-state buffers; RPORT clears the STATUS bit on a data read.

Part (d): interlocked-handshake timing. Reading the given data trace, Q7–Q0 holds a stable value, then changes to $A7, and later to $29. Each new value appears because a VALID edge from the keyboard clocked the data register — so a rising VALID edge is drawn at each Q7–Q0 transition, and this same edge sets STATUS to 1. The interface answers each VALID with an ACK pulse (interlocked). When the CPU issues RPORT to read the data, that strobe clears STATUS back to 0. The two required arrows therefore point (1) from the VALID edge to the Q7–Q0 change it causes, and (2) from the RPORT pulse down to the STATUS bit it clears.

Fig Q6.2 — Interlocked-handshake waveforms. Arrow (1): VALID transition loads Q₇–Q₀ and sets STATUS. Arrow (2): the RPORT read clears STATUS.

Question 6 — final results
Quantity	Result
PSTATUS	A₁₅A₁₄′A₁₃A₁₂′A₁₁′A₀′
PDATA	A₁₅A₁₄′A₁₃A₁₂′A₁₁′A₀
RSTATUS	PSTATUS · (R/W̅) · E
RPORT	PDATA · (R/W̅) · E
VALID (H1)	Clocks data + status flip-flops (sets STATUS = 1)
RPORT role	Enables data buffers and clears STATUS bit on read

Topic. Memory-mapped I/O address decoding on the 68HC11, read-strobe generation, and interlocked-handshake data capture.

Key relations. Partial (block) decode uses only the address bits constant across the block; a read strobe = decode · R/W̅ · E (E defines the half-cycle data window); interlocked handshake pairs VALID (source) with ACK (receiver); a status flag is set by the data-load clock and cleared by the CPU read.

Why this works. The exam's “fewest lines” instruction is the tell for partial decoding: because A10–A1 are don't-cares inside the 2 KB block, they must be left out of the decode, and the entire block aliases onto the two registers — which is acceptable precisely because the specification only forbids responses outside the block. Gating with E is what gives the strobe its half-cycle width automatically, since the HC11 holds E high for the data phase of every bus cycle. The status handshake is self-consistent: the VALID edge both captures the byte and raises the flag, and the CPU's own read (RPORT) tears the flag down, so the flag is a faithful “unread data present” indicator with no software bookkeeping.

Common pitfall. Fully decoding all sixteen address bits — that violates “fewest lines” and would place the registers at a single address rather than the intended block, and it needlessly adds gates. The other classic slip is clearing STATUS with the wrong signal: it must be cleared by the data read (RPORT), not by RSTATUS (which merely lets the CPU inspect the flag), otherwise the flag is destroyed before the data is fetched.

Source. Cady, M68HC11 Software and Hardware Engineering, ch. 8 (memory and I/O decoding) and ch. 9 (parallel I/O handshaking); Hamacher et al., Computer Organization and Embedded Systems 6th ed., §3.1–3.3 (memory-mapped I/O and interface registers).

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