Start/stop 3-bit synchronous counter: 22-Elec-A4 Digital Systems and Computers, May 2018, Q2

Question 2: Start/stop 3-bit synchronous counter (12 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A full 3-bit binary up-count $000\!\to\!111$ then wrap, built from positive-edge-triggered JK flip-flops with $Q_C$ the MSB and $Q_A$ the LSB. Part (b) adds a synchronous COUNT ENABLE (CTE) that pauses and later resumes the count with the state preserved.

Find. (a) the JK input equations and the counter schematic; (b) the modification that makes CTE gate the count without losing the current value.

Approach. Use the JK toggle mode ($J=K=1\Rightarrow$ toggle). A binary up-counter toggles stage $n$ exactly when all lower stages are 1, so drive each stage's tied $J,K$ with the AND of the lower bits. For CTE, AND that toggle condition with CTE so a LOW enable forces $J=K=0$ (hold) — the clock is never gated.

Derive the toggle conditions. In a binary up-count, bit $Q_A$ flips every clock; $Q_B$ flips when $Q_A=1$; $Q_C$ flips when $Q_A\!\cdot\!Q_B=1$. With JK flip-flops tied $J=K$ (toggle when 1, hold when 0): $$J_A=K_A=1,\qquad J_B=K_B=Q_A,\qquad J_C=K_C=Q_A\cdot Q_B.$$
Verify against the excitation requirement. At state $011$ the next state is $100$: $Q_A$ must toggle ($1\!\to\!0$, need $J_A K_A$ toggle ✓), $Q_B$ toggles ($1\!\to\!0$, condition $Q_A=1$ ✓), $Q_C$ toggles ($0\!\to\!1$, condition $Q_A Q_B=1$ ✓). All eight transitions check, and $111\!\to\!000$ follows because every toggle condition is satisfied at $111$.

(a) 3-bit synchronous up-counter. All flip-flops share the clock (synchronous); each stage's $J$ and $K$ are tied together and driven by the AND of the lower bits.

Add the COUNT ENABLE. AND every toggle input with CTE so the effective conditions become $$J_A=K_A=\text{CTE},\quad J_B=K_B=\text{CTE}\cdot Q_A,\quad J_C=K_C=\text{CTE}\cdot Q_A\cdot Q_B.$$ When $\text{CTE}=1$ the equations reduce to the part-(a) counter; when $\text{CTE}=0$ every $J=K=0$, so on each clock edge all flip-flops hold and the stored count is frozen.
Confirm clean resume. Because the clock is left running and only the data inputs are gated, the flip-flops keep their last value while paused. When CTE returns HIGH the toggle conditions are re-enabled and counting continues from the held state — no glitch, no lost or skipped count, unlike a scheme that gates the clock (which risks runt pulses).

(b) Same counter with CTE. Each stage's toggle input is ANDed with CTE (the enable ripples through the carry AND-chain). Clock is untouched, so the count holds when CTE=0 and resumes from where it stopped.

Question 2 — counter input equations
Stage	Part (a): free-running	Part (b): with CTE
$Q_A$ (LSB)	$J_A=K_A=1$	$J_A=K_A=\text{CTE}$
$Q_B$	$J_B=K_B=Q_A$	$J_B=K_B=\text{CTE}\cdot Q_A$
$Q_C$ (MSB)	$J_C=K_C=Q_A Q_B$	$J_C=K_C=\text{CTE}\cdot Q_A Q_B$

Topic: Synchronous binary counters and synchronous count-enable.

Key relations: JK characteristic $Q^+ = J\overline{Q}+\overline{K}Q$; toggle mode $J=K=1$; up-count carry chain $T_n=\prod_{i<n}Q_i$.

Why this works: In a synchronous counter every flip-flop is clocked simultaneously, so there is no ripple delay and the next state is a pure combinational function of the present state. A bit must invert exactly when all lower bits are 1 (the point at which adding one carries into it), which is precisely the AND of the lower outputs. Gating that AND with an enable is the textbook way to pause a counter; it keeps the clock edge aligned across the chip and preserves state because a JK with $J=K=0$ holds.

Common pitfall: gating the clock instead of the data inputs. A gated clock can produce partial/runt edges and clock-skew between stages, and is bad synchronous-design practice; enabling through $J,K$ avoids it. A second trap is forgetting to AND CTE into the top stage — if $Q_C$'s toggle omitted CTE, a paused counter sitting at $011$ or $111$ would keep flipping $Q_C$.

Source: Wakerly, Digital Design: Principles and Practices 5th ed., §11.4–11.5 (synchronous counters, enables); Mano & Ciletti §6.4.

Question 2 of 6: Start/stop 3-bit synchronous counter

Question 2: Start/stop 3-bit synchronous counter (12 marks)