22-Elec-A4 Digital Systems and Computers · May 2018
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
National Exams — May 2018 · 16-Elec-A4 Digital Systems & Computers. Closed book, 3 hours. Six questions, 12 marks each; the rubric requires any five, but all six are solved here as a study resource. Approved Casio/Sharp calculator permitted. A Boolean-identity table and the flip-flop excitation table are supplied with the paper (reproduced where used).
Reference texts. M. M. Mano & M. D. Ciletti, Digital Design (6th ed.) — number systems, Boolean minimization, sequential logic; J. F. Wakerly, Digital Design: Principles and Practices (5th ed.) — counters, registers, PLDs; C. Hamacher, Z. Vranesic, S. Zaky & N. Manjikian, Computer Organization and Embedded Systems (6th ed.) — parallel I/O, handshaking, memory-mapped ports; Motorola M68HC11 Reference Manual — port addressing and instruction set.
Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.
(a) Parallel-to-serial ⇒ the transmitting unit. A serial port moves data one bit at a time along a single line, whereas the CPU/bus inside the machine presents a whole byte in parallel. On the sending side the transmitter must therefore accept the byte in parallel from the data bus, then emit it one bit per bit-time onto the line. That is exactly a parallel-load, serial-out (parallel-to-serial) shift register: the byte is loaded into all stages at once, and successive clocks shift it out of the end. This is the heart of the transmit path of a UART.
(b) Serial-to-parallel ⇒ the receiving unit. On the receiving side the bits arrive one at a time on the line and must be re-assembled into a byte the CPU can read in one bus cycle. The receiver clocks each incoming bit into a shift register (serial-in), and after the full word has arrived the register's stages are read out in parallel. This serial-in, parallel-out (serial-to-parallel) register is the core of the UART receive path. In short, the two conversions are mirror images: the transmitter serializes (parallel→serial), the receiver deserializes (serial→parallel).
(c) A 4-bit bidirectional (universal) shift register. A single register can do both jobs if each D flip-flop is preceded by a 2:1 multiplexer selected by a MODE line. In load mode each mux passes its own parallel input $P_i$, so the four bits $P_0\!\ldots\!P_3$ are captured in one clock (parallel load — the entry point for parallel-to-serial). In shift mode each mux passes the previous stage's output, so data marches $Q_0\!\to\!Q_1\!\to\!Q_2\!\to\!Q_3$ one place per clock; the first stage takes the serial input SI (serial entry for serial-to-parallel) and the last stage's $Q_3$ is the serial output SO. The four stage outputs $Q_0\!\ldots\!Q_3$ are permanently available as the parallel outputs.
Loading $P_0\!\ldots\!P_3$ then selecting shift converts parallel→serial at SO; feeding bits into SI while shifting, then reading $Q_0\!\ldots\!Q_3$, converts serial→parallel. Terminals identified: (i) serial input = SI at the first mux's shift port; (ii) serial output = SO $=Q_3$; (iii) parallel inputs = $P_0,P_1,P_2,P_3$ at the mux load ports; (iv) parallel outputs = $Q_0,Q_1,Q_2,Q_3$.
