22-Elec-A5 Electronics · December 2014
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Paper format: National Exams, December 2014 — 07-Elec-A5 Electronics. Closed book, 3 hours; a non-communicating calculator is permitted. Answer all FIVE questions (20 marks each). Unless stated otherwise op-amps are ideal and the supplies are ±15 V.
Reference texts: A. S. Sedra & K. C. Smith, Microelectronic Circuits (7th ed., Oxford) — Ch. 3–4 (diodes, rectifiers/clamps), Ch. 7–8 (MOS amplifiers & biasing), Ch. 13–14 (CMOS logic inverter, VTC), Ch. 2 (op-amp circuits, instrumentation amplifier); R. L. Boylestad & L. Nashelsky, Electronic Devices and Circuit Theory (rectifiers, clampers).
Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.
Given. A complementary CMOS inverter (PMOS $M_2$ pull-up, NMOS $M_1$ pull-down), common gate $=v_{IN}$, common drain $=v_{OUT}$, supply $V_{DD}$. Device thresholds $V_{Tn}$ and $-|V_{Tp}|$. No numeric $V_{DD}$ or device sizes are given, so the answer is symbolic; the plotted VTC below is drawn for the matched, symmetric case ($V_{DD}=5$ V, $V_{Tn}=|V_{Tp}|=1$ V, $k_n=k_p$) for concreteness.
Find. The VTC and, marked on it, $V_{OH},V_{OL},V_{IL},V_{IH}$, the noise margins, and the transistor operating mode in each of the five regions.
Approach. Sweep $v_{IN}$ from 0 to $V_{DD}$ and track which device conducts and in what mode; the boundaries define the five regions and the logic levels.
At the rails only one transistor conducts and it carries no current, so the output is pulled hard to a rail: $\boxed{V_{OH}=V_{DD},\quad V_{OL}=0}$ (part c). As $v_{IN}$ increases the inverter passes through five regions, tabulated below with the device modes (part e).
| Region | Input range | NMOS $M_1$ | PMOS $M_2$ | Output |
|---|---|---|---|---|
| I | $0\le v_{IN}\lt V_{Tn}$ | cut-off | triode | $V_{OH}=V_{DD}$ |
| II | $V_{Tn}\le v_{IN}\lt V_M$ | saturation | triode | high, falling |
| III | $v_{IN}=V_M$ | saturation | saturation | steep transition |
| IV | $V_M\lt v_{IN}\le V_{DD}-|V_{Tp}|$ | triode | saturation | low, falling |
| V | $v_{IN}\gt V_{DD}-|V_{Tp}|$ | triode | cut-off | $V_{OL}=0$ |
The switching threshold $V_M$ (where $v_{OUT}=v_{IN}$, both devices saturated) follows from equating the saturation currents:
$$V_M=\frac{V_{Tn}+\sqrt{k_p/k_n}\,\bigl(V_{DD}-|V_{Tp}|\bigr)}{1+\sqrt{k_p/k_n}},\qquad k=k_n'\tfrac{W}{L}.$$
For matched devices ($k_n=k_p$, $V_{Tn}=|V_{Tp}|=V_t$) this reduces to $V_M=V_{DD}/2$. The logic input levels $V_{IL},V_{IH}$ are the two unity-gain ($\mathrm{d}v_{OUT}/\mathrm{d}v_{IN}=-1$) points; for the matched inverter the standard results are (part d):
$$\boxed{V_{IL}=\frac{3V_{DD}+2V_t}{8},\qquad V_{IH}=\frac{5V_{DD}-2V_t}{8}}.$$
The noise margins are then (part b) $\;NM_H=V_{OH}-V_{IH}\;$ and $\;NM_L=V_{IL}-V_{OL}$. For the illustrative numbers ($V_{DD}=5$, $V_t=1$): $V_M=2.5$ V, $V_{IL}=2.125$ V, $V_{IH}=2.875$ V, giving the symmetric result $NM_H=NM_L=2.125$ V. The complete VTC with every level and region labelled is shown below.
Check: the exam gives thresholds only symbolically and no $V_{DD}$ or device sizes, so $V_M$, $V_{IL}$, $V_{IH}$ and the margins are expressed symbolically; the plotted values assume a matched inverter with $V_{DD}=5$ V and $V_{Tn}=|V_{Tp}|=1$ V purely to make the sketch concrete.
| Level | Symbolic | Illustrative (VDD=5, Vt=1) |
|---|---|---|
| $V_{OH}$ | $V_{DD}$ | 5.000 V |
| $V_{OL}$ | 0 | 0 V |
| $V_M$ | $V_{DD}/2$ (matched) | 2.500 V |
| $V_{IL}$ | $(3V_{DD}+2V_t)/8$ | 2.125 V |
| $V_{IH}$ | $(5V_{DD}-2V_t)/8$ | 2.875 V |
| $NM_L=V_{IL}-V_{OL}$ | $(3V_{DD}+2V_t)/8$ | 2.125 V |
| $NM_H=V_{OH}-V_{IH}$ | $(3V_{DD}+2V_t)/8$ | 2.125 V |
