Question 5 of 5: Common-Collector (Emitter-Follower) Design
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format: National Exams, 07-Elec-A5 Electronics, December 2015 — closed book, non-communicating calculator permitted, 3 hours. Answer all FIVE questions (20 marks each). In schematics ground and chassis are common; op-amps are ideal and supplies are ±15 V unless a question states otherwise.
Reference texts: A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. (diode wave-shaping & limiters Ch. 4; MOSFET amplifiers Ch. 7; BJT amplifiers Ch. 6–7; op-amp applications Ch. 2).
Given. An emitter follower on ±5 V rails: base fed from vs through RS–C1 with RB to ground; collector to RC and AC-bypassed to the +5 V rail by CC; output taken at the emitter through CE, with RE to −5 V.
Given data
Quantity
Value
β
100
VBE(on)
0.7 V
VCE(sat)
0.3 V
RS, RB
100 Ω each
Rails / target
±5 V, IE = 2 mA
Find. (a) RE and RC; (b) output resistance Ro at the emitter; (c) maximum undistorted peak-to-peak swing.
Figure 5.1 — Emitter follower. The collector is AC-grounded by CC to the +5 V rail, so it is a true common-collector stage; the output at the emitter is coupled out through CE.
Approach. Fix the DC operating point from IE = 2 mA to size RE; choose RC to keep Q1 active with symmetric headroom. Then find the output resistance looking into the emitter, and finally the clipping limits that bound the undistorted swing.
(a) DC bias — RE. The base current $I_B=I_E/(\beta+1)=2/101=19.8\ \mu$A drops only $I_B R_B\approx2$ mV across RB, so $V_B\approx0$ and $V_E=V_B-V_{BE}=-0.7$ V. With the emitter returned to −5 V,
(a) DC bias — RC. The collector carries $I_C=\alpha I_E=\tfrac{100}{101}(2)=1.98$ mA. Since CC makes the collector an AC ground, RC only sets the DC collector voltage; choosing $V_C=+3.9$ V gives symmetric headroom (see part c) and keeps $V_{CE}=V_C-V_E=4.6$ V well above saturation:
(b) Output resistance. With $V_T=25$ mV, $r_e=V_T/I_E=25/2=12.5\ \Omega$. Looking back from the emitter, the base network reflects down by $\beta+1$: the base sees $R_S\|R_B=100\|100=50\ \Omega$ (input source zeroed), so
(c) Maximum undistorted swing. The emitter sits at −0.7 V. Two limits bound its excursion: on the positive swing the transistor saturates when $V_{CE}\!\to\!V_{CE(sat)}$, i.e. at $V_E=V_C-0.3=+3.6$ V — a headroom of $3.6-(-0.7)=4.3$ V; on the negative swing the transistor cuts off as the emitter approaches the −5 V rail, a headroom of $-0.7-(-5)=4.3$ V. Choosing VC=3.9 V made these equal, so the maximum symmetric swing is
Check / design choice: because CC AC-grounds the collector, RC plays no role in the signal path and its value is a bias/headroom decision. Any RC ≲ 560 Ω (so that VC ≥ 3.9 V) yields the same 8.6 Vpp maximum swing, now limited symmetrically by emitter cutoff at −5 V. A larger RC lowers VC and reduces the positive headroom.