Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format: National Exams, 07-Elec-A5 Electronics, May 2015 — closed book, non-communicating calculator permitted, 3 hours. Answer all FIVE questions (20 marks each). Op-amps ideal, supplies ±15 V unless a question states otherwise.
Reference texts: A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. (diodes Ch. 4; MOS & BJT amplifiers Ch. 5–7; op-amp applications Ch. 2 & 13).
Given. An n-channel common-source stage biased by divider $R_1$–$R_2$, drain resistor $R_D$, and source resistor $R_S$ bypassed by $C_2$. Target specifications and device data:
Given data
$R_{in}$
$R_{out}$
$I_{bias}$
$V_{DD}$
$V_{TH}$
$\mu_nC_{ox}\tfrac{W}{L}$
50 kΩ
6 kΩ
0.5 mA
10 V
1 V
1 mA/V$^2$
Find. $R_1$, $R_2$, $R_D$ and $R_S$ (and the resulting operating point).
Q5: common-source stage. R₁‖R₂ set R in and the gate bias; R₊ sets R out and drain current; R S (bypassed by C₂) sets the source bias.
Approach. Fix the drain current from $I_{bias}$ and get $V_{GS}$; set $R_D$ from the output resistance; choose the gate bias for good headroom and back out $R_S$; finally split the divider to hit $R_{in}$.
Overdrive and $V_{GS}$. The bias current is the drain current, $I_D=I_{bias}=0.5$ mA. In saturation $I_D=\tfrac12\mu_nC_{ox}\tfrac{W}{L}(V_{GS}-V_{TH})^2$, so $$V_{OV}=\sqrt{\frac{2I_D}{\mu_nC_{ox}W/L}}=\sqrt{\frac{2(0.5)}{1}}=1\ \text{V}\ \Rightarrow\ V_{GS}=V_{TH}+V_{OV}=2\ \text{V}.$$ The transconductance is $g_m=2I_D/V_{OV}=1\ \text{mA/V}$.
Drain resistor from $R_{out}$. With $\lambda=0$ the device output resistance $r_o=\infty$, so the resistance seen at the output is just $R_D$: $$\boxed{R_D=R_{out}=6\ \text{k}\Omega}.$$ The DC drain voltage is $V_D=V_{DD}-I_DR_D=10-0.5(6)=7\ \text{V}.$
Gate bias and $R_S$. Place the gate at mid-supply, $V_G=V_{DD}/2=5$ V, for a symmetric, bias-stable divider. Then the source sits at $V_S=V_G-V_{GS}=5-2=3$ V, and since the source current equals $I_D$, $$\boxed{R_S=\frac{V_S}{I_D}=\frac{3}{0.5\ \text{mA}}=6\ \text{k}\Omega}.$$
Divider from $R_{in}$. The gate draws no current and $C_1$ blocks DC, so $R_{in}=R_1\parallel R_2=50\ \text{k}\Omega$. The mid-supply gate needs $V_G=V_{DD}R_2/(R_1+R_2)=5$ V, i.e. $R_1=R_2$; therefore $R_1\parallel R_2=R_1/2=50\ \text{k}\Omega$ gives $$\boxed{R_1=R_2=100\ \text{k}\Omega}.$$
Saturation check. $V_{DS}=V_D-V_S=7-3=4\ \text{V}\gt V_{OV}=1\ \text{V}$, so the MOSFET is safely in saturation as required.
Check. The specifications fix $R_D$, $V_{GS}$ and $R_1\parallel R_2$ but leave the DC gate voltage free; the mid-supply choice $V_G=V_{DD}/2=5$ V is a standard design decision that yields clean, well-conditioned values ($R_1=R_2=100$ kΩ, $R_S=6$ kΩ) and ample saturation margin. A different $V_G$ would rescale $R_1,R_2,R_S$ while still meeting $R_{in}$, $R_{out}$ and $I_{bias}$.
