22-Elec-A5 Electronics · May 2016

Question 4 of 5: Common-Source Amplifier Bias Point

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

National Exam — 07-Elec-A5 Electronics — May 2016. Closed-book; non-communicating calculator permitted; three hours. Five questions, 20 marks each — all five constitute a complete paper, so every question is solved below. Op-amps are ideal with supply rails of ±15 V unless a question states otherwise.

Reference texts (22-Elec-A5 Electronics): A. S. Sedra & K. C. Smith, Microelectronic Circuits, 7th/8th ed. (Oxford) — diodes (Ch. 4), MOSFETs and biasing (Ch. 5/7), op-amp circuits (Ch. 2), signal generators / wave-shaping (Ch. 17), MOS logic inverters (Ch. 14); R. C. Jaeger & T. N. Blalock, Microelectronic Circuit Design (McGraw-Hill).

Check / figure note: every schematic below was redrawn from the printed figures of the paper. Where the paper omits a numeric supply (Q1), the transfer curve is drawn to scale for an illustrative V_DD = 5 V and the symbolic result is stated alongside.

Question 4: Common-Source Amplifier Bias Point (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given.

Given data (Question 4)
Parameter	Value	Parameter	Value
$R_1$	100 kΩ	$R_2$	100 kΩ
$R_D$	6 kΩ	$R_S$	6 kΩ
$V_{TH}$	1 V	$\lambda$	0
$V_{DD}$	10 V	$K'_n(W/L)$	1 mA/V$^2$

Find. the gate/source/drain node voltages and every branch current at the DC operating point.

Figure 4. Self-biased common-source stage; capacitors are open at DC, so only the R₁/R₂ divider and the R_D–M₁–R_S branch carry DC.

Approach. At DC the coupling/bypass capacitors are open, so the gate sits at the divider voltage and no gate current flows; write the source-degeneration bias equation, solve the resulting quadratic for $I_D$, keep the root with $V_{GS}\gt V_{TH}$, then back out every node voltage.

Gate voltage (divider, no gate current). $$V_G=V_{DD}\frac{R_2}{R_1+R_2}=10\cdot\frac{100}{200}=\boxed{5\ \text{V}}$$ The divider itself draws $I_{bias}=V_{DD}/(R_1+R_2)=10/200\text{ k}=0.05$ mA.
Bias equation with source degeneration. $V_{GS}=V_G-I_DR_S$ and (saturation, $\lambda=0$) $I_D=\tfrac12K(V_{GS}-V_{TH})^2$. Substituting ($I_D$ in mA, $R_S=6$ kΩ): $I_D=\tfrac12(1)(5-6I_D-1)^2=\tfrac12(4-6I_D)^2$.
Solve the quadratic. $18I_D^2-25I_D+8=0\Rightarrow I_D=\dfrac{25\pm7}{36}=0.889\ \text{or}\ 0.5$ mA. The 0.889 mA root gives $V_{GS}=-0.33$ V < $V_{TH}$ (device off) — reject. Hence $$\boxed{I_D=0.5\ \text{mA}},\qquad V_{GS}=5-6(0.5)=2\ \text{V}.$$
Node voltages. $$V_S=I_DR_S=0.5(6)=3\ \text{V},\quad V_D=V_{DD}-I_DR_D=10-0.5(6)=\boxed{7\ \text{V}}=v_{OUT}\text{ (DC)}.$$
Confirm saturation. $V_{DS}=V_D-V_S=4$ V and $V_{GS}-V_{TH}=1$ V; since $V_{DS}\ge V_{GS}-V_{TH}$ the transistor is saturated, as assumed. (Transconductance $g_m=K(V_{GS}-V_{TH})=1$ mA/V for later small-signal work.)

Question 4 — DC operating point
Quantity	Value
Gate $V_G$	5 V
Source $V_S$	3 V
Drain $V_D=v_{OUT}$	7 V
$V_{GS}$ / $V_{DS}$	2 V / 4 V
Drain current $I_D$ (through $R_D,M_1,R_S$)	0.5 mA
Divider current ($R_1,R_2$)	0.05 mA

Topic. Four-resistor (divider + source-degeneration) MOSFET bias.

Key relations. $V_G=V_{DD}R_2/(R_1+R_2)$; $V_{GS}=V_G-I_DR_S$; $I_D=\tfrac12K(V_{GS}-V_{TH})^2$; saturation check $V_{DS}\ge V_{GS}-V_{TH}$.

Why this works. The large divider fixes the gate at a stiff 5 V while drawing negligible current; the source resistor provides negative feedback ($I_D\!\uparrow\Rightarrow V_S\!\uparrow\Rightarrow V_{GS}\!\downarrow$), so the operating point is set by the resistors, not by the poorly controlled $K$ — the whole point of this bias topology.

Common pitfall. Keeping the algebraic root that violates $V_{GS}\gt V_{TH}$, or forgetting to confirm saturation before trusting the square-law current. Both are settled by the two inequality checks above.

Source. Sedra & Smith, Microelectronic Circuits, §7.4 (biasing MOS amplifiers); Jaeger & Blalock §4.

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