Common-emitter (PNP) amplifier design: 22-Elec-A5 Electronics, May 2018, Q3

Question 3: Common-emitter (PNP) amplifier design

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

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CC through R_E (bypassed by C₃), base set by the R₁/R₂ divider, collector to ground through R_C, output coupled to R_L through C₂." style="max-width:460px;width:100%;height:auto">

Question 3 — PNP common-emitter stage: emitter to +V_CC through R_E (bypassed by C₃), base set by the R₁/R₂ divider, collector to ground through R_C, output coupled to R_L through C₂.

Given. A PNP common-emitter stage whose emitter degeneration R_E is fully bypassed at mid-band by C₃; the base is biased by the R₁/R₂ divider. Early voltage infinite, so $r_o=\infty$.

Given data
Parameter	Value
β	100
$V_{EB(on)}$, $V_{EC(sat)}$	0.7 V, 0.3 V
$V_{CC}$, $R_L$, $R_E$	10 V, 10 kΩ, 1 kΩ
Target $I_E$, gain	2 mA, 100 V/V

Find. R₁, R₂, R_C (part a); the output resistance R_O (part b); the maximum undistorted peak-to-peak swing at the output (part c).

Approach. Fix the operating point from I_E, set R_C from the bypassed-emitter gain, choose the divider for a stiff bias, then read R_O from the collector node and the swing from the AC load line.

Check: two modelling choices are stated up front. (i) $V_T=25\ \text{mV}$ is assumed (room-temperature convention). (ii) The source resistance $R_i$ is not given a numerical value, so the specified gain is taken at the transistor base (input attenuation from $R_i$ neglected), which is what fixes $R_C$. (iii) The bias-divider current is a design degree of freedom; a stiff-bias rule $I_{R_2}\approx10\,I_B$ is used. Any comparable stiff choice is acceptable.

Operating point (part a). With $\beta=100$, $I_C=\dfrac{\beta}{\beta+1}I_E=\dfrac{100}{101}(2\ \text{mA})=1.98\ \text{mA}$, $I_B=I_C/\beta=19.8\ \mu\text{A}$, and the transconductance is $g_m=I_C/V_T=1.98\ \text{mA}/25\ \text{mV}=79.2\ \text{mA/V}.$
Set R_C from the gain. With R_E bypassed and $r_o=\infty$, the mid-band gain magnitude is $|A_v|=g_m\,(R_C\parallel R_L)$. Requiring 100 V/V:$$R_C\parallel R_L=\frac{100}{g_m}=\frac{100}{79.2\ \text{mA/V}}=1.26\ \text{k}\Omega \;\Rightarrow\; R_C=\left(\frac{1}{1262.5}-\frac{1}{10000}\right)^{-1}=\boxed{1.44\ \text{k}\Omega}.$$
Bias voltages. The emitter sits one $I_ER_E$ drop below the rail and the base one $V_{EB}$ below the emitter (PNP):$$V_E=V_{CC}-I_ER_E=10-(2\ \text{mA})(1\ \text{k}\Omega)=8\ \text{V},\quad V_B=V_E-V_{EB}=7.3\ \text{V}.$$
Size the divider. Choosing $I_{R_2}=10\,I_B=198\ \mu\text{A}$ and noting that for a PNP the base current adds into the divider node ($I_{R_1}=I_{R_2}+I_B$):$$R_2=\frac{V_{CC}-V_B}{I_{R_2}}=\frac{2.7}{198\ \mu\text{A}}=\boxed{13.6\ \text{k}\Omega},\quad R_1=\frac{V_B}{I_{R_2}+I_B}=\frac{7.3}{217.8\ \mu\text{A}}=\boxed{33.5\ \text{k}\Omega}.$$
Output resistance (part b). Looking back into the collector, the transistor is a current source with $r_o=\infty$, so the amplifier output resistance is simply R_C:$$R_O=R_C\parallel r_o=R_C=\boxed{1.44\ \text{k}\Omega}.$$
Maximum undistorted swing (part c). The DC collector voltage is $V_C=I_CR_C=(1.98\ \text{mA})(1.44\ \text{k}\Omega)=2.86\ \text{V}$, giving $V_{EC}=V_E-V_C=5.14\ \text{V}$ (well into the active region). On the AC load line ($R_C\parallel R_L=1.26\ \text{k}\Omega$) the two clipping limits are:$$\text{toward saturation: }(V_E-V_{EC(sat)})-V_C=7.7-2.86=4.84\ \text{V},$$$$\text{toward cutoff: }I_C(R_C\parallel R_L)=(1.98\ \text{mA})(1.26\ \text{k}\Omega)=2.50\ \text{V}.$$ The smaller half-swing (cutoff, 2.50 V) sets the symmetric limit, so the maximum undistorted output is$$V_{o,pp}=2\times2.50=\boxed{5.0\ \text{V (peak-to-peak)}}.$$

Question 3 — results
Quantity	Value
$R_C$	1.44 kΩ
$R_1$ (base–ground)	33.5 kΩ
$R_2$ (V_CC–base)	13.6 kΩ
$R_O$	1.44 kΩ
Max undistorted swing	5.0 V peak-to-peak

Topic. Biasing and load-line design of a common-emitter (PNP) amplifier with a bypassed emitter.

Key relations. Bias: $I_C=\frac{\beta}{\beta+1}I_E$, $g_m=I_C/V_T$. Gain (R_E bypassed): $|A_v|=g_m(R_C\parallel R_L)$. Output resistance $R_O=R_C\parallel r_o$. Symmetric swing = $2\min[(V_E-V_{EC(sat)})-V_C,\;I_C(R_C\parallel R_L)]$.

Why this works. C₃ shorts R_E at signal frequencies, so the emitter is an AC ground and the full $g_m$ appears in the gain; the DC path through R_E still stabilises the operating point. The swing is limited by whichever of saturation or cutoff the AC load line reaches first.

Common pitfall. Using the DC load line (through R_C alone) for the swing. The signal sees $R_C\parallel R_L$, a steeper AC load line, so the cutoff-side headroom is smaller than the DC value — use the AC load line.

Source. Sedra & Smith, Microelectronic Circuits, 8th ed., Ch. 6–7 (BJT biasing, CE amplifier, signal swing).

Question 3 of 5: Common-emitter (PNP) amplifier design

Question 3: Common-emitter (PNP) amplifier design